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Issue No. 10 - October (1970 vol. 19)
ISSN: 0018-9340
pp: 896-902
V. Batra , IEEE
An asynchronous unit delay is an n-input n-output asynchronous sequential circuit such that the present value of the output n-tuple is equal to the value of the input n-tuple prior to the last input change. The delay is of significance as a building block for shift register realizations of asynchronous circuits.
Asynchronous, equivalent flow table, fundamental mode, pulse controlled.
V. Batra, "Design of Asynchronous Unit Delays", IEEE Transactions on Computers, vol. 19, no. , pp. 896-902, October 1970, doi:10.1109/T-C.1970.222796
96 ms
(Ver )