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The advent of large-scale integration of logic circuits requires the definition of digital computer structure in terms of large functional arrays of logic of very few types. This paper describes a single-package arithmetic processor called the arithmetic building element (ABE). The ABE accepts operands in either conventional or signed-digit radix-r representation and produces signed-digit results, which the ABE can reconvert to conventional form. Radix 16 is chosen for illustrations. Arrays of ABE's may be arranged to implement unit- time parallel addition, all-combinational multiplication, and more complex functions which are presently computed by subroutines. To facilitate such arithmetic design, a graph model is developed which permits a translation of the given arithmetical algorithm into an interconnection diagram of ABE's. The design procedure is illustrated by an array for polynomial evaluation. Speed, cost, and roundoff error of the array are considered. A computer program has been written for the automatic translation of the algorithm graph to an interconnection graph, and for the evaluation of the cost and speed for a given polynomial degree and a given precision requirement.
Arithmetic array modeling, arithmetic building element, arithmetic processors, computer-aided processor design, graph models of arithmetic, microelectronic building block, polynomial evaluation array, signed-digit number systems.

n. Chin Tung and A. AviZienis, "A Universal Arithmetic Building Element (ABE) and Design Methods for Arithmetic Processors," in IEEE Transactions on Computers, vol. 19, no. , pp. 733-745, 1970.
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