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ABSTRACT
This paper is an attempt to develop minimization algorithms for switching circuits based on Reed-Muller canonic forms. In particular, algorithms are presented for obtaining minimal modulo 2 or complement modulo 2 sum-of- products (or sums) expressions of any arbitrary single-output or multiple-output switching function with fixed polarities of the input variables.
INDEX TERMS
APL, cellular logic arrays, maximal cliques of a graph, miniimization algorithms, modulo 2 sum-of- products (or sums), Reed-Muller canonic forms.
CITATION
A. Mukhopadhyay, G. Schmitz, "Minimization of Exclusive or and Logical Equivalence Switching Circuits", IEEE Transactions on Computers, vol. 19, no. , pp. 132-140, February 1970, doi:10.1109/T-C.1970.222878
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