Issue No.10 - October (1969 vol.18)
W.T. Lynch , IEEE
The worst-case output voltage ratio V<inf>s</inf>(1)<inf>min</inf>/V<inf>s</inf>(0)<inf>max</inf>is derived for a resistor memory matrix having a finite resistance ratio for the bit elements. It is found that the resistance ratio need not be large, and ratios greater than ten are usually sufficient. Input power and output voltage tradeoffs are also discussed.
Fixed memories, READ-only memories, resistor matrices, switchable resistor matrices, worst-case analysis of resistor matrices.
W.T. Lynch, "Worst-Case Analysis of a Resistor Memory Matrix", IEEE Transactions on Computers, vol.18, no. 10, pp. 940-942, October 1969, doi:10.1109/T-C.1969.222549