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Issue No. 09 - September (1969 vol. 18)
ISSN: 0018-9340
pp: 800-816
R.L. Davis , IEEE
This paper describes the design of the processing element (PE) of I IV, a parallel processing computer consisting of 256 PE's, each with an associated 2048 word memory. Each PE-memory combination with its data-dependent controls is a computer in itself, devoid of those controls common to all PE-memory combinations, such as instruction decoding, instruction look-ahead, etc.
Computer arithmetic, ILLIAC IV, medium-scale integration, parallel processing.

R. Davis, "The ILLIAC IV Processing Element," in IEEE Transactions on Computers, vol. 18, no. , pp. 800-816, 1969.
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