Issue No. 08 - August (1969 vol. 18)
A high-speed carry circuit for binary parallel adders is described. The circuit consists of emitter followers connected in series to form a transmission path for carry signals obtained from the individual bits of the adder.
Binary parallel adders, computer simulation, logic circuitry, operational results, simple fast carry.
C. Weller, "A High-Speed Carry Circuit for Binary Adders," in IEEE Transactions on Computers, vol. 18, no. , pp. 728-732, 1969.