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Issue No. 08 - August (1969 vol. 18)
ISSN: 0018-9340
pp: 728-732
ABSTRACT
A high-speed carry circuit for binary parallel adders is described. The circuit consists of emitter followers connected in series to form a transmission path for carry signals obtained from the individual bits of the adder.
INDEX TERMS
Binary parallel adders, computer simulation, logic circuitry, operational results, simple fast carry.
CITATION
C.W. Weller, "A High-Speed Carry Circuit for Binary Adders", IEEE Transactions on Computers, vol. 18, no. , pp. 728-732, August 1969, doi:10.1109/T-C.1969.222755
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