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The ALERT system converts preliminary high-level descriptions of computers into logic. The input to ALERT depicts the architecture of a proposed machine in a form of Iverson notation. As output, the architecture is "compiled" into Boolean equations, which may then be converted into standard computer circuits.
Architecture, automatic logic generation, compiler of computers, design automation, high-level computer description, Iverson notation, structural implementation of algorithms.
null Sih-Chin Yang, T.D. Friedman, "Methods Used in an Automatic Logic Design Generator (ALERT)", IEEE Transactions on Computers, vol. 18, no. , pp. 593-614, July 1969, doi:10.1109/T-C.1969.222727
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