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A modification of the conventional design method for pulse-type sequential logic is developed in which threshold gates are used in all of the combinational portions of the circuit. The canonical configuration, memory element employed, tabular design aids, etc., found in the conventional method were changed as necessary in order to use more effectively the unique properties possessed by threshold elements. A theorem providing insight for threshold gate realization is given and a classification of sequential functions is discussed in order to facilitate the understanding and use of the new process. Finally, examples are presented showing a significant advantage of the present method in both gate and transistor economy over conventional design.
Logical design, realizability, sequence classification, sequential networks, switching circuit synthesis, threshold logic.
D.F. Wann, R.M. Kline, "Threshold Logic Design of Pulse-Type Sequential Networks", IEEE Transactions on Computers, vol. 18, no. , pp. 459-465, May 1969, doi:10.1109/T-C.1969.222686
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