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TABLE OF CONTENTS
Issue No. 01 - January (vol. 18)
ISSN: 0018-9340
Papers

Logic Design Automation of Fan-In Limited NAND Networks (PDF)

D.L. Dietmeyer , Department of Electrical Engineering, University of Wisconsin, Madison, Wis.
Yueh-Hsung Su , Department of Electrical Engineering, School of Engineering and Sciences, New York University, New York, N. Y.
pp. 11-22

Module Clustering to Minimize Delay in Digital Networks (PDF)

E.L. Lawler , Systems Engineering Laboratory, University of Michigan, Ann Arbor, Mich.
K.N. Levitt , Stanford Research Institute, Menlo Park, Calif.
J. Turner , Stanford Research Institute, Menlo Park, Calif.
pp. 47-57

Computer Reduction of Two-Level, Multiple-Output Switching Circuits (Abstract)

Yueh-Hsung Su , Department of Electrical Engineering, New York University, New York, N. Y.
D.L. Dietmeyer , Departmentof Electrical Engineering, University of Wisconsin, Madison, Wis.
pp. 58-63

A Simplified Analysis of Processor "Look-Ahead" and Simultaneous Operation of a Multi-Module Main Memory (Abstract)

J.E. Shemer , Scientific Data Systems, El Segundo, Calif.
S.C. Gupta , Inforrnation and Control Sciences Center, Institute of Technology, Southern Methodist University, Dallas, Tex.
pp. 64-71

Subtraction by Minuend Complementation (PDF)

G.G. Langdon , Department of Mechanical Engineering, University of Sydney, Sydney, Australia
pp. 74-76
Papers

IEEE Computer Group (PDF)

pp. c2

Author's Reply<sup>3</sup> (PDF)

N. Deo , Jet Propulsion Laboratory California Institute of Technology
pp. 80

Comment on "A Variable Counter Design Technique" (PDF)

T.A. Taebel , Elec. Engrg. Dept. General Motors Institute
pp. 80

Contributors (PDF)

pp. 81-82

R69-1 Transport Time-Delay Simulation for Transmission Line Representation (PDF)

R.D. Benham , Process Simulation and Analysis Dept. Battelle Northwest
pp. 83

Information for Authors (PDF)

pp. 104

Blank Page (PDF)

pp. 104
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