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Issue No. 01 - January (1969 vol. 18)
ISSN: 0018-9340
pp: 71-74
With a suitable adder organization it is possible to overlap the adder operation during a binary multiplication and significantly decrease the overall multiplication time. The method is explained and a prototype multiplier described. The new technique provides a very economical method of obtaining a reasonably fast multiplier.
Concurrent ADD cycles, parallel binary multiplier, propagating adder control signals, synchronous adder.
P.M. Fenwick, "Binary Multiplication with Overlapped Addition Cycles", IEEE Transactions on Computers, vol. 18, no. , pp. 71-74, January 1969, doi:10.1109/T-C.1969.222527
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