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This paper focuses attention upon the design of a processor and memory system which is structured to achieve a satisfactory balance of processor speed and memory speed when both the processor and input?output controller are simultaneously competing for memory service. A mathematical model is developed to investigate the degree to which the processor is capable of overlapping memory references with instruction execution as a function of respective cycle times, the number of instruction "look-aheads," the number of independent memory modules, and input?output traffic. Utilizing this model, design trade-offs and performance indices are graphically examined for a hypothetical system.
Interlaced memories, mathematical modeling, multi-module memory, overlapped memory access, processor "look-ahead, " simultaneous I/O and instruction processing.
S.C. Gupta, J.E. Shemer, "A Simplified Analysis of Processor "Look-Ahead" and Simultaneous Operation of a Multi-Module Main Memory", IEEE Transactions on Computers, vol. 18, no. , pp. 64-71, January 1969, doi:10.1109/T-C.1969.222526
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