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ABSTRACT
An algorithm which reduces the number of gates and connections (diodes) in two-level, multiple-output combinational logic networks is presented and compared with conventional minimization procedures.
INDEX TERMS
Algorithm, combinational logic synthesis, logic design automation, multiple-output switching functions, reduction of two-level logic.
CITATION
D.L. Dietmeyer, null Yueh-Hsung Su, "Computer Reduction of Two-Level, Multiple-Output Switching Circuits", IEEE Transactions on Computers, vol. 18, no. , pp. 58-63, January 1969, doi:10.1109/T-C.1969.222525
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