Issue No. 01 - January (1969 vol. 18)
null Yueh-Hsung Su , IEEE
An algorithm which reduces the number of gates and connections (diodes) in two-level, multiple-output combinational logic networks is presented and compared with conventional minimization procedures.
Algorithm, combinational logic synthesis, logic design automation, multiple-output switching functions, reduction of two-level logic.
D. Dietmeyer and n. Yueh-Hsung Su, "Computer Reduction of Two-Level, Multiple-Output Switching Circuits," in IEEE Transactions on Computers, vol. 18, no. , pp. 58-63, 1969.