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An important aspect of the packaging of digital networks is the allocation of logic gates to modules such that a predetermined objective function is minimized. In order to develop techniques for this partitioning of a logic network we have considered the following problem: Given an acyclic combinational network composed of various primitive blocks such as NOR gates, assume that a maximum of M gates can be "clustered" together into larger modules, and that a maximum of P pins can be accommodated in each larger module. Assume also that in a network composed of such larger modules, no delay is encountered on the interconnections linking two gates internal to a module and a delay of one time unit is encountered on interconnections linking two gates in different modules . Find an easily applied algorithm that will result in a network such that the maximum delay through the network is minimized.
Graph decomposition, logic partitioning, minimization of longest delay.
E.L. Lawler, K.N. Levitt, J. Turner, "Module Clustering to Minimize Delay in Digital Networks", IEEE Transactions on Computers, vol. 18, no. , pp. 47-57, January 1969, doi:10.1109/T-C.1969.222524
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