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Abstract?A computer-oriented algorithm for synthesizing combinational logic circuits from a collection of functionally packaged circuits is developed. The algorithm uses a hierarchy of "goals" in an iterative decision process in a manner similar to that employed by theorem proving and gamne playing programs. With each iteration a set of "tasks" finds the circuit package which satisfies the highest level goal while meeting circuit constraints.
Index terms?Circuit constraints, combinational logic synthesis, decomposition, design algorithm, design goals, logic design automation, module library.
D.L. Dietmeyer, P.R. Schneider, "An Algorithm for Synthesis of Multiple-Output Combinational Logic", IEEE Transactions on Computers, vol. 17, no. , pp. 117-128, February 1968, doi:10.1109/TC.1968.227399
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