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Issue No. 01 - January (1968 vol. 17)
ISSN: 0018-9340
pp: 18-26
Janusz A. Brzozowski , Dept. of Elec. Engrg., University of Ottawa, Ottawa, Ontario, Canada; Department of Applied Analysis and Computer Science, University of Waterloo, Waterloo, Ontario, Canada.
Shanker Singh , Dept. of Elec. Engrg., University of Ottawa, Ottawa, Ontario, Canada.
An asynchronous unit delay is an n input n output asynchronous sequential circuit in which the present value of the output n-tuple is equal to the value of the input n-tuple prior to the last input change. This paper considers the problem of determining when a fundamental mode flow table is realizable as a feedback-free connection of asynchronous unit delays. It is shown that such a realization exists if and only if the flow table is asynchronous definite, where the asynchronous definite property is a modification of the definite property of synchronous sequential machines. A straightforward method of realizing asynchronous definite flow tables without critical races by feedback-free circuits of asynchronous unit delays and combinational gates is developed. The use of asynchronous unit delays for definite tables avoids complicated secondary assignment problems, results in circuits with very simple structure, and brings closer the theories of synchronous and asynchronous sequential machines.
Janusz A. Brzozowski, Shanker Singh, "Definite Asynchronous Sequential Circuits", IEEE Transactions on Computers, vol. 17, no. , pp. 18-26, January 1968, doi:10.1109/TC.1968.5008864
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