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Issue No. 11 - Nov. (2018 vol. 26)
ISSN: 1063-8210
pp: 2335-2344
Makoto Yabuuchi , Renesas Electronics Corporation, Kodaira, Japan
Yasumasa Tsukamoto , Renesas Electronics Corporation, Kodaira, Japan
Hidehiro Fujiwara , Renesas Electronics Corporation, Kodaira, Japan
Miki Tanaka , Renesas Electronics Corporation, Kodaira, Japan
Shinji Shinji , Renesas Electronics Corporation, Kodaira, Japan
Koji Nii , Renesas Electronics Corporation, Kodaira, Japan
ABSTRACT
We demonstrate a 1-read/1-write two-port (2P) embedded static random access memory macro based on 8T SRAM bitcell with an effective scheme for design of testability. To achieve a smaller macro area, a differential sense amplifier is introduced to read out the data, where the reference voltage for reading 0/1 data is generated by an unselected bitcell array. In addition, we propose a screening test circuit for read disturbance and wordline coupling noise. A 512-kbit 2P SRAM macro using 28-nm high-K/metal gate bulk CMOS technology has been designed, confirming experimentally that the worst minimum operation voltage ( $_$V_{\text {min}}$_$ ) can be reproduced by our test circuit. Bit density of 3.16 Mb/mm2 was achieved.
INDEX TERMS
Random access memory, Couplings, Degradation, Timing, Logic gates, Very large scale integration, Monte Carlo methods
CITATION

M. Yabuuchi, Y. Tsukamoto, H. Fujiwara, M. Tanaka, S. Shinji and K. Nii, "A 28-nm 1R1W Two-Port 8T SRAM Macro With Screening Circuitry Against Read Disturbance and Wordline Coupling Noise Failures," in IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 26, no. 11, pp. 2335-2344, 2018.
doi:10.1109/TVLSI.2018.2864267
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