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Issue No. 09 - Sept. (2018 vol. 26)
ISSN: 1063-8210
pp: 1802-1806
Juhyung Hong , Department of Electrical and Electronic Engineering, Yonsei University, Seoul, South Korea
Sangwoo Han , Department of Electrical and Electronic Engineering, Yonsei University, Seoul, South Korea
Young Min Park , Department of Electrical and Electronic Engineering, Yonsei University, Seoul, South Korea
Eui-Young Chung , Department of Electrical and Electronic Engineering, Yonsei University, Seoul, South Korea
ABSTRACT
The performance bottleneck of NAND flash-based storage devices (NFSDs) is mainly due to the slow NAND flash memories (NFMs). One of the well-known techniques for overcoming the bottleneck is an interleaving technique. This technique aims to maximize the utilization of high-speed channels by allowing slow NFMs to operate in parallel. Typically, NFSDs hierarchically apply the multilevel interleaving technique—channel, way, and die-level. While channel/way-level interleaving has already matured, die-level interleaving faces practical difficulties. The most critical issue is that it is not easy to identify individual die status because multiple dies in a package share a status pin, because of the form factor and cost issues of NFSDs. For this reason, NFSD has to issue a read status (RS) command to check the die status, which requires nonmarginal performance overhead. Moreover, the RS overhead attenuates the advantages of channel sneaking (CS) introduced in this brief to accelerate interleaving. To tackle this issue, we propose interrupt-based CS (ICS) that maximizes the impact of die-level interleaving while paying marginal overhead for identifying the die status. ICS performs on-demand die-status monitoring with minor modification of the NFM interface. We prove its effectiveness by conducting experiments in which ICS improves the performance by 19.8% over the typical scheme.
INDEX TERMS
Pins, Computer architecture, Bandwidth, Timing, Data transfer, Very large scale integration
CITATION

J. Hong, S. Han, Y. M. Park and E. Chung, "ICS: Interrupt-Based Channel Sneaking for Maximally Exploiting Die-Level Parallelism of NAND Flash-Based Storage Devices," in IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 26, no. 9, pp. 1802-1806, 2018.
doi:10.1109/TVLSI.2018.2824818
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