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TABLE OF CONTENTS
Issue No. 03 - March (vol. 23)
ISSN: 1063-8210

Table of contents (PDF)

pp. C1-C4

Level-Converting Retention Flip-Flop for Reducing Standby Power in ZigBee SoCs (Abstract)

Jung-Hyun Park , School of Electrical and Electronic Engineering, Yonsei University, Seoul, Korea
Heechai Kang , Samsung Electronics Company, Ltd., Gyeonggi-Do, Korea
Dong-Hoon Jung , School of Electrical and Electronic Engineering, Yonsei University, Seoul, Korea
Kyungho Ryu , School of Electrical and Electronic Engineering, Yonsei University, Seoul, Korea
Seong-Ook Jung , School of Electrical and Electronic Engineering, Yonsei University, Seoul, Korea
pp. 413-421

A Boosting Pass Gate With Improved Switching Characteristics and No Overdriving for Programmable Routing Switch Based on Crystalline In-Ga-Zn-O Technology (Abstract)

Yuki Okamoto , Semiconductor Energy Laboratory Company, Ltd., Atsugi, Japan
Takashi Nakagawa , Semiconductor Energy Laboratory Company, Ltd., Atsugi, Japan
Takeshi Aoki , Semiconductor Energy Laboratory Company, Ltd., Atsugi, Japan
Masataka Ikeda , Semiconductor Energy Laboratory Company, Ltd., Atsugi, Japan
Munehiro Kozuma , Semiconductor Energy Laboratory Company, Ltd., Atsugi, Japan
Takeshi Osada , Semiconductor Energy Laboratory Company, Ltd., Atsugi, Japan
Yoshiyuki Kurokawa , Semiconductor Energy Laboratory Company, Ltd., Atsugi, Japan
Takayuki Ikeda , Semiconductor Energy Laboratory Company, Ltd., Atsugi, Japan
Naoto Yamade , Semiconductor Energy Laboratory Company, Ltd., Atsugi, Japan
Yutaka Okazaki , Semiconductor Energy Laboratory Company, Ltd., Atsugi, Japan
Hidekazu Miyairi , Semiconductor Energy Laboratory Company, Ltd., Atsugi, Japan
Masahiro Fujita , VLSI Design and Education Center, University of Tokyo, Tokyo, Japan
Jun Koyama , Semiconductor Energy Laboratory Company, Ltd., Atsugi, Japan
Shunpei Yamazaki , Semiconductor Energy Laboratory Company, Ltd., Atsugi, Japan
pp. 422-434

Low-Cost On-Chip Clock Jitter Measurement Scheme (Abstract)

Martin Omana , University of Bologna, Bologna, Italy
Daniele Rossi , University of Bologna, Bologna, Italy
Daniele Giaffreda , University of Bologna, Bologna, Italy
Cecilia Metra , University of Bologna, Bologna, Italy
T. M. Mak , GlobalFoundries, Sunnyvale, CA, USA
Asifur Rahman , Intel Corporation, Portland, OR, USA
Simon Tam , Intel Corporation, Santa Clara, CA, USA
pp. 435-443

A self-powered high-efficiency rectifier with automatic resetting of transducer capacitance in piezoelectric energy harvesting systems (Abstract)

Xuan-Dien Do , Nice Laboratory, Korea Advanced Institute of Science and Technology, Daejeon, Korea
Huy-Hieu Nguyen , Samsung Company, Ltd., Seoul, Korea
Seok-Kyun Han , Nice Laboratory, Korea Advanced Institute of Science and Technology, Daejeon, Korea
Dong Sam Ha , Department of Electrical and Computer Engineering, Virginia Polytechnic Institute and State University, Blacksburg, VA, USA
Sang-Gug Lee , Nice Laboratory, Korea Advanced Institute of Science and Technology, Daejeon, Korea
pp. 444-453

Novel reconfigurable hardware architecture for polynomial matrix multiplications (Abstract)

Soydan Redif , Department of Electrical and Electronics Engineering, European University of Lefke, Gemikonagi, Turkey
Server Kasap , Department of Computer Science, University of Paderborn, Paderborn, Germany
pp. 454-465

Diagnosis and Layout Aware (DLA) Scan Chain Stitching (Abstract)

Jing Ye , State Key Laboratory of Computer Architecture, Institute of Computing Technology, Chinese Academy of Sciences, Beijing, China
Yu Huang , Mentor Graphics Corporation, Wilsonville, OR, USA
Yu Hu , State Key Laboratory of Computer Architecture, Institute of Computing Technology, Chinese Academy of Sciences, Beijing, China
Wu-Tung Cheng , Mentor Graphics Corporation, Wilsonville, OR, USA
Ruifeng Guo , Synopsys Inc., Wilsonville, OR, USA
Liyang Lai , Mentor Graphics Corporation, Wilsonville, OR, USA
Ting-Pu Tai , Mentor Graphics Corporation, Wilsonville, OR, USA
Xiaowei Li , State Key Laboratory of Computer Architecture, Institute of Computing Technology, Chinese Academy of Sciences, Beijing, China
Weipin Changchien , Taiwan Semiconductor Manufacturing Company, Hsinchu, Taiwan
Daw-Ming Lee , Taiwan Semiconductor Manufacturing Company, Hsinchu, Taiwan
Ji-Jan Chen , Taiwan Semiconductor Manufacturing Company, Hsinchu, Taiwan
Sandeep C. Eruvathi , Taiwan Semiconductor Manufacturing Company, Hsinchu, Taiwan
Kartik K. Kumara , Taiwan Semiconductor Manufacturing Company, Hsinchu, Taiwan
Charles Liu , Taiwan Semiconductor Manufacturing Company, Hsinchu, Taiwan
Sam Pan , Taiwan Semiconductor Manufacturing Company, Hsinchu, Taiwan
pp. 466-479

A GPU-accelerated parallel shooting algorithm for analysis of radio frequency and microwave integrated circuits (Abstract)

Xue-Xin Liu , Synopysis Corporation, Mountain View, CA, USA
Hao Yu , School of Electrical and Electronic Engineering, Nanyang Technological University, Singapore
Sheldon X.-D. Tan , Department of Electrical Engineering, University of California at Riverside, Riverside, CA, USA
pp. 480-492

Economizing TSV Resources in 3-D Network-on-Chip Design (Abstract)

Ying Wang , SKL Computer Architecture, ICT, Chinese Academy of Sciences, Beijing, China
Yin-He Han , SKL Computer Architecture, ICT, Chinese Academy of Sciences, Beijing, China
Lei Zhang , SKL Computer Architecture, ICT, Chinese Academy of Sciences, Beijing, China
Bin-Zhang Fu , SKL Computer Architecture, ICT, Chinese Academy of Sciences, Beijing, China
Cheng Liu , SKL Computer Architecture, ICT, Chinese Academy of Sciences, Beijing, China
Hua-Wei Li , SKL Computer Architecture, ICT, Chinese Academy of Sciences, Beijing, China
Xiaowei Li , SKL Computer Architecture, ICT, Chinese Academy of Sciences, Beijing, China
pp. 493-506

Demonstrating HW-SW transient error mitigation on the single-chip cloud computer data plane (Abstract)

Dimitrios Rodopoulos , Micro Laboratory, School of Electrical and Computer Engineering, National Technical University of Athens, Athens, Greece
Antonis Papanikolaou , Micro Laboratory, School of Electrical and Computer Engineering, National Technical University of Athens, Athens, Greece
Francky Catthoor , imec, Leuven, Belgium
Dimitrios Soudris , Micro Laboratory, School of Electrical and Computer Engineering, National Technical University of Athens, Athens, Greece
pp. 507-519

Runtime Thermal Management for 3-D Chip-Multiprocessors With Hybrid SRAM/MRAM L2 Cache (Abstract)

Seunghan Lee , Department of Electrical Engineering, Korea Advanced Institute of Science and Technology, Daejeon, Korea
Kyungsu Kang , Samsung Electronics, Hwaseongsi, Korea
Chong-Min Kyung , Department of Electrical Engineering, Korea Advanced Institute of Science and Technology, Daejeon, Korea
pp. 520-533

Super Fast Physics-Based Methodology for Accurate Memory Yield Prediction (Abstract)

Rajiv V. Joshi , IBM TJ Watson Laboratories, Yorktown Heights, NY, USA
Keunwoo Kim , IBM TJ Watson Laboratories, Yorktown Heights, NY, USA
Rouwaida Kanj , American University of Beirut, Beirut, Lebanon
Ajay N. Bhoj , IBM TJ Watson Laboratories, Yorktown Heights, NY, USA
Matthew M. Ziegler , IBM TJ Watson Laboratories, Yorktown Heights, NY, USA
Phil Oldiges , IBM TJ Watson Laboratories, Yorktown Heights, NY, USA
Pranita Kerber , IBM TJ Watson Laboratories, Yorktown Heights, NY, USA
Robert Wong , IBM Technology, Hopewell Junction, NY, USA
Terence Hook , IBM Technology, Hopewell Junction, NY, USA
Sudesh Saroop , IBM Technology, Hopewell Junction, NY, USA
Carl Radens , IBM TJ Watson Laboratories, Yorktown Heights, NY, USA
Chun-Chen Yeh , IBM TJ Watson Laboratories, Yorktown Heights, NY, USA
pp. 534-543

Aging-Aware Reliable Multiplier Design With Adaptive Hold Logic (Abstract)

Ing-Chao Lin , Department of Computer Science and Information Engineering, National Cheng Kung University, Tainan, Taiwan
Yu-Hung Cho , Welltrend Semiconductor, Inc., Kaohsiung, Taiwan
Yi-Ming Yang , VIA Technology, Inc., New Taipei City, Taiwan
pp. 544-556

A 16-mW 8-Bit 1-GS/s Digital-Subranging ADC in 55-nm CMOS (Abstract)

Yung-Hui Chung , Department of Electronic and Computer Engineering, National Taiwan University of Science and Technology, Taipei, Taiwan
Jieh-Tsorng Wu , Department of Electronics Engineering and Institute of Electronics, National Chiao-Tung University, Hsinchu, Taiwan
pp. 557-566

Designing a SAR-based all-digital delay-locked loop with constant acquisition cycles using a resettable delay line (Abstract)

Chia-Yu Yao , Department of Electrical Engineering, National Taiwan University of Science and Technology, Taipei, Taiwan
Yung-Hsiang Ho , Department of Electrical Engineering, National Taiwan University of Science and Technology, Taipei, Taiwan
Yi-Yao Chiu , Department of Electrical Engineering, National Taiwan University of Science and Technology, Taipei, Taiwan
Rong-Jyi Yang , MediaTek Inc., Taipei, Taiwan
pp. 567-574

Parallel Thermal Analysis of 3-D Integrated Circuits With Liquid Cooling on CPU-GPU Platforms (Abstract)

Xue-Xin Liu , Department of Electrical Engineering, University of California at Riverside, Riverside, CA, USA
Kuangya Zhai , Department of Computer Science and Technology, Tsinghua University, Beijing, China
Zao Liu , Department of Electrical Engineering, University of California at Riverside, Riverside, CA, USA
Kai He , Department of Electrical Engineering, University of California at Riverside, Riverside, CA, USA
Sheldon X.-D. Tan , Department of Electrical Engineering, University of California at Riverside, Riverside, CA, USA
Wenjian Yu , Department of Computer Science and Technology, Tsinghua University, Beijing, China
pp. 575-579

Resistive Open Faults Detectability Analysis and Implications for Testing Low Power Nanometric ICs (Abstract)

Mohamed Tagelsir Mohammadat , Department of Electrical and Electronic Engineering, Universiti Teknologi Petronas, Tronoh, Malaysia
Noohul Basheer Zain Ali , Department of Electrical and Electronic Engineering, Universiti Teknologi Petronas, Tronoh, Malaysia
Fawnizu Azmadi Hussin , Department of Electrical and Electronic Engineering, Universiti Teknologi Petronas, Tronoh, Malaysia
Mark Zwolinski , Department of Electronics and Computer Science, University of Southampton, Southampton, U.K.
pp. 580-583

A Synergetic Use of Bloom Filters for Error Detection and Correction (Abstract)

Pedro Reviriego , Universidad Antonio de Nebrija, Madrid, Spain
Salvatore Pontarelli , National Interuniversity Consortium for Telecommunications, Rome, Italy
Juan Antonio Maestro , Universidad Antonio de Nebrija, Madrid, Spain
Marco Ottavi , University of Rome Tor Vergata, Rome, Italy
pp. 584-587

An 11.5 Gb/s 1/4th Baud-Rate CTLE and Two-Tap DFE With Boosted High Frequency Gain in 110-nm CMOS (Abstract)

Yong-Hun Kim , Department of Electrical Engineering and Computer Science, Korea Advanced Institute of Science and Technology, Daejeon, Korea
Young-Ju Kim , Department of Electrical Engineering and Computer Science, Korea Advanced Institute of Science and Technology, Daejeon, Korea
Tae-Ho Lee , Department of Electrical Engineering and Computer Science, Korea Advanced Institute of Science and Technology, Daejeon, Korea
Lee-Sup Kim , Department of Electrical Engineering and Computer Science, Korea Advanced Institute of Science and Technology, Daejeon, Korea
pp. 588-592

Skewed-Load Test Cubes Based on Functional Broadside Tests for a Low-Power Test Set (Abstract)

Irith Pomeranz , School of Electrical and Computer Engineering, Purdue University, West Lafayette, IN, USA
pp. 593-597

A 3.6-mW 50-MHz PN Code Acquisition Filter via Statistical Error Compensation in 180-nm CMOS (Abstract)

Eric P. Kim , Department of Electrical and Computer Engineering, University of Illinois at Urbana-Champaign, Urbana, IL, USA
Daniel J. Baker , Department of Electrical and Computer Engineering, University of Illinois at Urbana-Champaign, Urbana, IL, USA
Sriram Narayanan , Department of Electrical and Computer Engineering, University of Illinois at Urbana-Champaign, Urbana, IL, USA
Naresh R. Shanbhag , Department of Electrical and Computer Engineering, University of Illinois at Urbana-Champaign, Urbana, IL, USA
Douglas L. Jones , Department of Electrical and Computer Engineering, University of Illinois at Urbana-Champaign, Urbana, IL, USA
pp. 598-602

Arithmetic-based binary-to-RNS converter modulo {2n±k} for jn-bit dynamic range (Abstract)

Pedro Miguens Matutino , High Institute of Engineering of Lisbon, Instituto de Engenharia de Sistemas e Computadores Investigação e Desenvolvimento em Lisboa, Instituto Superior Técnico, Universidade de Lisboa, Lisbon, Portugal
Ricardo Chaves , Instituto de Engenharia de Sistemas e Computadores Investigação e Desenvolvimento em Lisboa, Instituto Superior Técnico, Universidade de Lisboa, Lisbon, Portugal
Leonel Sousa , Instituto de Engenharia de Sistemas e Computadores Investigação e Desenvolvimento em Lisboa, Instituto Superior Técnico, Universidade de Lisboa, Lisbon, Portugal
pp. 603-607
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