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Variations of power and ground levels affect very large scale integration circuit performance. Trends in device technology and in packaging have necessitated a revision in conventional delay models. In particular, simple scalable models are needed to predict delays in the presence of uncorrelated power and ground noise. In this paper, we analyze the effect of such noise-on-signal propagation through a buffer and present simple, closed-form formulas to estimate the corresponding change of delay. The model captures both positive (slowdown) and negative (speedup) delay changes. It is consistent with short-channel MOSFET behavior, including carrier velocity saturation effects. An application shows that repeater chains using buffers instead of inherently faster inverters tend to have superior supply-level-induced jitter characteristics. The expressions can be used in any existing circuit performance optimization design flow or can be combined into any delay calculations as a correction factor.
delays, integrated circuit noise, VLSI, MOS integrated circuits, circuit optimisation, integrated circuit packaging,buffer delay change, ground noise, very large scale integration, closed-form formulas, short-channel MOSFET behavior, carrier velocity saturation, repeater chains, jitter characteristics, circuit performance optimization, packaging, delay models, uncorrelated power noise, noise-on-signal propagation,Circuit noise, Circuit optimization, Delay estimation, Very large scale integration, Packaging, Predictive models, Delay effects, Propagation delay, MOSFET circuits, Repeaters
"Buffer delay change in the presence of power and ground noise", IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 11, no. , pp. 461-473, June 2003, doi:10.1109/TVLSI.2003.812310
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