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ABSTRACT
This paper presents an intellectual property (IP)-based system-on-chip (SoC) synthesis framework focusing on how to select IPs from different sources and how to integrate the selected IPs using on-chip buses. In order to synthesize an on-chip bus-based SoC architecture using IPs with imprecise design costs, we propose a possibilistic mixed integer linear programming (PMILP) model, which is converted into an equivalent mixed integer linear programming (MILP) model without increasing the computational complexity. Then, the equivalent MILP model is solved to decide whether each IP is selected or not, and to locate the selected IP on the optimal on-chip bus of a hierarchical bus architecture that consists of on-chip buses with different bus attributes. Experimental results on an MP3 decoding system show that the IP-centric design space with uncertainty can be successfully explored using the proposed scheme.
INDEX TERMS
system-on-chip, linear programming, integer programming, possibility theory, fuzzy set theory, fuzzy logic, circuit complexity, VLSI, industrial property, hardware-software codesign, embedded systems,intellectual property, system-on-chip synthesis, imprecise design costs, on-chip buses, bus-based architecture, possibilistic mixed integer linear programming, equivalent mixed integer linear programming, computational complexity, MP3 decoding system, W-centric design space, hierarchical bus architecture, reusable building blocks, communication synthesis, design space exploration, design reuse, fuzzy programming,Costs, System-on-a-chip, Intellectual property, Mixed integer linear programming, Uncertainty, Computer architecture, Digital audio players, Decoding, Signal synthesis, Digital signal processing
CITATION
"Exploiting intellectual properties with imprecise design costs for system-on-chip synthesis", IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 10, no. , pp. 240-252, June 2002, doi:10.1109/TVLSI.2002.1043327
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