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ISSN: 2332-7766
Michael J. Doyle , School of Computer Science and Statistics, Trinity College Dublin, Ireland. (e-mail: mjdoyle@tcd.ie).
ABSTRACT
The ever-increasing demands of computer graphics applications have motivated the evolution of computer graphics hardware over the last twenty years. Early commodity graphics hardware was largely based on fixed-function components offering little flexibility. The gradual replacement of fixed-function hardware with more general-purpose instruction processors, has enabled GPUs to deliver visual experiences more tailored to specific applications. This trend has culminated in modern GPUs essentially being programmable stream processors, capable of supporting a wide variety of applications in and outside of computer graphics. However, the growing concern of power efficiency in modern processors, coupled with an increasing demand for supporting next-generation graphics pipelines, has re-invigorated the debate on the use of fixed-function accelerators in these platforms. In this paper, we conduct a study of a heterogeneous, system-on-chip solution for the construction of a highly important data structure for computer graphics: the bounding volume hierarchy. This design incorporates conventional CPU cores alongside a fixed-function accelerator prototyped on a reconfigurable logic fabric. Our study supports earlier, simulation-only studies which argue for the introduction of this class of accelerator in future graphics processors.
INDEX TERMS
Volume Visualization, Ray Tracing, Hardware Architecture, Reconfigurable Hardware
CITATION
Michael J. Doyle, Ciaran Tuohy, Michael Manzke, "Evaluation of a BVH Construction Accelerator Architecture for High-Quality Visualization", IEEE Transactions on Multi-Scale Computing Systems, vol. , no. , pp. 1, 5555, doi:10.1109/TMSCS.2017.2695338
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