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Integrated circuits (ICs) are now designed and fabricated in a globalized multi-vendor environment making them vulnerable to malicious design changes, the insertion of hardware trojans/malware and intellectual property (IP) theft. Algorithmic reverse engineering of digital circuits can mitigate these concerns by enabling analysts to detect malicious hardware, verify the integrity of ICs and detect IP violations. In this paper, we present a set of algorithms for the reverse engineering of digital circuits starting from an unstructured netlist and resulting in a high-level netlist with components such as register files, counters, adders and subtractors. Our techniques require no manual intervention and experiments show that they determine the functionality of more than 45% and up to 93% of the gates in each of the test circuits that we examine. We also demonstrate that our algorithms are scalable to real designs by experimenting with a very large, highly-optimized systemon- chip (SoC) design with over 375,000 combinational elements. Our inference algorithms cover 68% of the gates in this SoC. We also demonstrate that our algorithms are effective in aiding a human analyst detect hardware trojans in an unstructured netlist.

S. Malik et al., "Reverse Engineering Digital Circuits Using Structural and Functional Analyses," in IEEE Transactions on Emerging Topics in Computing.
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