The Community for Technology Leaders
Workload Characterization, Annual IEEE International Workshop (2004)
Austin, TX, USA
Oct. 25, 2004 to Oct. 25, 2004
ISBN: 0-7803-8828-3
TABLE OF CONTENTS

Foreword (PDF)

pp. iv
Papers

Breaker page (PDF)

pp. 0_2

Copyright page (PDF)

pp. ii

Reviewers (PDF)

pp. vi

Breaker page (PDF)

pp. 1

Breaker page (PDF)

pp. 2

Characterizing the impact of different memory-intensity levels (Abstract)

F. Rawson , Texas Univ., Austin, TX, USA
T. Keller , Texas Univ., Austin, TX, USA
A. Devgan , Texas Univ., Austin, TX, USA
R. Kotla , Texas Univ., Austin, TX, USA
S. Ghiasi , Texas Univ., Austin, TX, USA
pp. 3-10

On the extraction and analysis of prevalent dataflow patterns (Abstract)

P.G. Sassone , Sch. of Electr.&Comput. Eng., Georgia Inst. of Technol., Atlanta, GA, USA
D.S. Wills , Sch. of Electr.&Comput. Eng., Georgia Inst. of Technol., Atlanta, GA, USA
pp. 11-18

Evaluation of a speculative multithreading compiler by characterizing program dependences (Abstract)

A. Bhowmik , Dept. of Comput. Sci.&Autom., Indian Inst. of Sci., Bangalore, India
pp. 19-26

Breaker page (PDF)

pp. 27

Breaker page (PDF)

pp. 28

GENIUS: a generator of interactive user media sessions (Abstract)

J.M. Almeida , Dept. of Comput. Sci., Fed. Univ. of Minas Gerais, Belo Horizonte, Brazil
C. Ramos , Dept. of Comput. Sci., Fed. Univ. of Minas Gerais, Belo Horizonte, Brazil
I. Cunha , Dept. of Comput. Sci., Fed. Univ. of Minas Gerais, Belo Horizonte, Brazil
C. Costa , Dept. of Comput. Sci., Fed. Univ. of Minas Gerais, Belo Horizonte, Brazil
pp. 29-36

Micro-architectural anatomy of a commercial TCP/IP stack (Abstract)

R. Iyer , Commun. Technol. Lab., Intel Corp., Santa Clara, CA, USA
D. Newell , Commun. Technol. Lab., Intel Corp., Santa Clara, CA, USA
R. Illikkal , Commun. Technol. Lab., Intel Corp., Santa Clara, CA, USA
pp. 37-44

Breaker page (PDF)

pp. 45

Breaker page (PDF)

pp. 46

Does halting make hardware trace collection inaccurate? A study using Pentium 4 performance counters and SPEC2000 (Abstract)

J.K. Flanagan , Dept. of Comput. Sci., Brigham Young Univ., Provo, UT, USA
M. Watson , Dept. of Comput. Sci., Brigham Young Univ., Provo, UT, USA
pp. 47-54

Experiments with subsetting benchmark suites (Abstract)

K. De Bosschere , Dept. of Electron.&Inf. Syst., Ghent Univ., Netherlands
H. Vandierendonck , Dept. of Electron.&Inf. Syst., Ghent Univ., Netherlands
pp. 55-62

The USAR characterization model (Abstract)

W. Santos , Fed. Univ. of Minas Gerais, Brazil
W. Meira , Fed. Univ. of Minas Gerais, Brazil
G. Franco , Fed. Univ. of Minas Gerais, Brazil
A. Pereira , Fed. Univ. of Minas Gerais, Brazil
L. Silva , Fed. Univ. of Minas Gerais, Brazil
pp. 63-70

Breaker page (PDF)

pp. 71

Breaker page (PDF)

pp. 72

Evaluating performance of BLAST on Intel Xeon and Itanium2 processors (Abstract)

O. Celebioglu , Scalable Syst. Group, Dell, Round Rock, TX, USA
G. Kochhar , Scalable Syst. Group, Dell, Round Rock, TX, USA
R. Ali , Scalable Syst. Group, Dell, Round Rock, TX, USA
R. Radhakrishnan , Scalable Syst. Group, Dell, Round Rock, TX, USA
J. Hsieh , Scalable Syst. Group, Dell, Round Rock, TX, USA
pp. 81-88

Author index (PDF)

pp. 89-90

Breaker page (PDF)

pp. 91
102 ms
(Ver 3.3 (11022016))