The Community for Technology Leaders
VLSI, IEEE Computer Society Workshop on (2001)
Orlando, FL
Apr. 19, 2001 to Apr. 20, 2001
ISBN: 0-7695-1056-6
TABLE OF CONTENTS
•Emerging Trends in VLSI Systems

Towards a Very High Bandwidth Wireless Battery Powered Device (Abstract)

John Glossner , Sandbridge Technologies
David Routenberg , Sandbridge Technologies
Erdem Hokenek , Sandbridge Technologies
Mayan Moudgill , Sandbridge Technologies
Michael J. Schulte , Lehigh University
Pablo I. Balzola , Lehigh University
Stamatis Vassiliadis , Delft University of Technology
pp. 0003

Energy-Efficient Link Layer for Wireless Microsensor Networks (Abstract)

Eugene Shih , Massachusetts Institute of Technology
Benton H. Calhoun , Massachusetts Institute of Technology
SeongHwan Cho , Massachusetts Institute of Technology
Anantha P. Chandrakasan , Massachusetts Institute of Technology
pp. 0016
•System Level Design Examples

System Design of Low-Energy Wearable Computers with Wireless Networking (Abstract)

Asim Smailagic , Carnegie Mellon University
Daniel P. Siewiorek , Carnegie Mellon University
Matthew Ettus , Carnegie Mellon University
pp. 0025

A Multi-PLL Clock Distribution Architecture for Gigascale Integration (Abstract)

Martin Saint-Laurent , Intel Corporation
Madhavan Swaminathan , Georgia Institute of Technology
pp. 0030

Structural Design Composition for C++ Hardware Models (Abstract)

Frederic Doucet , University of California at Irvine
Vivek Sinha , University of California at Irvine
Rajesh Gupta , University of California at Irvine
pp. 0036

Design and Implementation of a Coarse-Grained Dynamically Reconfigurable Hardware Architecture (Abstract)

Jürgen Becker , Darmstadt University of Technology, Institute of Microelectronic Systems
Thilo Pionteck , Darmstadt University of Technology, Institute of Microelectronic Systems
Christian Habermann , Darmstadt University of Technology, Institute of Microelectronic Systems
Manfred Glesner , Darmstadt University of Technology, Institute of Microelectronic Systems
pp. 0041

A Heterogeneous Multiprocessor Architecture for Low-Power Audio Signal Processing Applications (Abstract)

Özgün Paker , Technical University of Denmark
Jens Sparsø , Technical University of Denmark
Niels Haandbæk , Oticon A/S
Mogens Isager , Oticon A/S
Lars Skovby Nielsen , Oticon A/S
pp. 0047
•Advanced VLSI Design

Application of Output Prediction Logic to Differential CMOS (Abstract)

Su Kio , University of Washington
Larry McMurhie , University of Washington
Carl Sechen , University of Washington
pp. 0057

Current Sensing Techniques for Global Interconnects in Very Deep Submicron(VDSM) CMOS (Abstract)

Atul Maheshwari , University of Massachusetts
Wayne Burleson , University of Massachusetts
pp. 0066

Built-In Self-Testable Date Path Synthesis (Abstract)

Laurence Tianruo Yang , St. Francis Xavier University
Jon Muzio , University of Victoria
pp. 0078
•Advanced Circuit Design

Load-Sensitive Flip-Flop Characterization (Abstract)

Seongmoo Heo , Massachusetts Institute of Technology
Krste Asanovic , Massachusetts Institute of Technology
pp. 0087

A Linear Threshold Gate Implementation in Single Electron Technology (Abstract)

Casper Lageweg , Delft University of Technology
Sorin Cotofana , Delft University of Technology
Stamatis Vassiliadis , Delft University of Technology
pp. 0093

Evaluating Metastability in Electronic Circuits for Random Number Generation (Abstract)

Shonda Walker , FAMU-FSU College of Engineering
Simon Foo , FAMU-FSU College of Engineering
pp. 0099

Improved Power Estimation For Behavioral and Gate Level Designs (Abstract)

Ronnie L. Wright , DCS Corporation, U.S. Army
Michael A. Shanblatt , Michigan State University
pp. 0102
•Low Power Design

VLIW Scheduling for Energy and Performance (Abstract)

A. Parikh , The Pennsylvania State University
M. Kandemir , The Pennsylvania State University
N. Vijaykrishnan , The Pennsylvania State University
M. J. Irwin , The Pennsylvania State University
pp. 0111

A Low-Energy Adaptive Bus Coding Scheme (Abstract)

Benjamin Bishop , University of Georgia
Anil Bahuman , University of Georgia
pp. 0118

LUT-Based FPGA Technology Mapping for Power Minimization with Optimal Depth (Abstract)

Hao Li , University of South Florida
Wai-Kei Mak , University of South Florida
Srinivas Katkoori , University of South Florida
pp. 0123
•Advances in Analog-to-Digital Converters Design

A 1-GSPS CMOS Flash A/D Converter for System-on-Chip Applications (Abstract)

Jincheol Yoo , The Pennsylvania State University
Kyusun Choi , The Pennsylvania State University
Ali Tangel , University of Kocaeli
pp. 0135

Transient Fault Sensitivity Analysis of Analog-to-Digital Converters (ADCs) (Abstract)

Mandeep Singh , University of Massachusetts
Ravinder Rachala , University of Massachusetts
Israel Koren , University of Massachusetts
pp. 0140
•Low-Power Design of ALUs

A Novel Architecture for Low-Power Design of Parallel Multipliers (Abstract)

Ayman A. Fayed , University of Louisiana at Lafayette
Magdy A. Bayoumi , University of Louisiana at Lafayette
pp. 0149

A Pipelined LNS ALU (Abstract)

Mark G. Arnold , University of Manchester Institute of Science and Technology and the University of Wyoming
pp. 0155
•Issues in System Design

A Hybrid Wave-Pipelined Network Router (Abstract)

José G. Delgado-Frias , University of Virginia
Jabulani Nyathi , State University of New York
pp. 0165

A Memory Management Approach for Efficient Implementation of Multimedia Kernels on Programmable Architectures (Abstract)

M. Dasigenis , Democritus University of Thrace
N. Kroupis , Democritus University of Thrace
A. Argyriou , Democritus University of Thrace
K. Tatas , Democritus University of Thrace
D. Soudris , Democritus University of Thrace
A. Thanailakis , Democritus University of Thrace
N. Zervas , University of Patras
pp. 0171

Author Index (PDF)

pp. 0177
103 ms
(Ver )