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2016 IEEE 34th VLSI Test Symposium (VTS) (2016)
Las Vegas, NV, USA
April 25, 2016 to April 27, 2016
ISSN: 2375-1053
ISBN: 978-1-4673-8453-7
TABLE OF CONTENTS

[Front cover] (PDF)

pp. c1

[Blank page] (PDF)

pp. 1

[Title page] (PDF)

pp. 1

Foreword (PDF)

pp. 1-2

Best paper award (PDF)

pp. 1-4

Keynote address: Challenges and opportunities in electrical characterization and test for 14nm and below (PDF)

Andrzej J. Strojwas , PDF Solutions, Inc., Keithley Professor Carnegie Mellon University, USA
Jacob Abraham , Cockrell Family Regents Chair in Engineering, University of Texas at Austin, USA
Hong Hao , Foundry Business Samsung Semiconductor Inc., USA
Max Shulaker , Stanford University, USA
pp. 1-2

A novel technique for interdependent trim code optimization (Abstract)

Pankaj Bongale , Texas Instruments (India) Pvt. Ltd., Bengaluru, India
Vinothkumar Sundaresan , Tessolve Services Pvt. Ltd., Bengaluru, India
Partha Ghosh , Eidgenssische Technische Hochschule (ETH), Zurich, Switzerland
Rubin Parekhji , Texas Instruments (India) Pvt. Ltd., Bengaluru, India
pp. 1-6

Infant mortality tests for analog and mixed-signal circuits (Abstract)

Suvadeep Banerjee , Georgia Institute of Technology
Suriyaprakash Natarajan , Intel Corporation
pp. 1-6

Wafer-level process variation-driven probe-test flow selection for test cost reduction in analog/RF ICs (Abstract)

Ali Ahmadi , Department of Electrical Engineering, The University of Texas at Dallas, Richardson, TX 75080
Amit Nahar , Texas Instruments Inc., 12500 TI Boulevard, MS 8741, Dallas, TX 75243
Bob Orr , Texas Instruments Inc., 12500 TI Boulevard, MS 8741, Dallas, TX 75243
Michael Past , Texas Instruments Inc., 12500 TI Boulevard, MS 8741, Dallas, TX 75243
Yiorgos Makris , Department of Electrical Engineering, The University of Texas at Dallas, Richardson, TX 75080
pp. 1-6

A convergent procedure for partially-reachable states (Abstract)

Irith Pomeranz , School of Electrical and Computer Engineering, Purdue University, West Lafayette, IN 47907, U.S.A.
pp. 1-6

Path constraint solving based test generation for observability-enhanced branch coverage (Abstract)

Yanhong Zhou , SKLCA, Institute of Computing Technology, Chinese Academy of Sciences, Beijing, China
Huawei Li , SKLCA, Institute of Computing Technology, Chinese Academy of Sciences, Beijing, China
Tiancheng Wang , SKLCA, Institute of Computing Technology, Chinese Academy of Sciences, Beijing, China
Bo Liu , Beijing Institute of Control Engineering, Beijing, China
Yingke Gao , Beijing Institute of Control Engineering, Beijing, China
Xiaowei Li , SKLCA, Institute of Computing Technology, Chinese Academy of Sciences, Beijing, China
pp. 1-6

WeSPer: A flexible small delay defect quality metric (Abstract)

Omar Al-Terkawi Hasib , Department of Electrical Engineering, École Polytechnique of Montréal, Montréal, Canada
Yvon Savaria , Department of Electrical Engineering, École Polytechnique of Montréal, Montréal, Canada
Claude Thibeault , Department of Electrical Engineering, École de technologie supérieure, Montréal, Canada
pp. 1-6

Consistency in wafer based outlier screening (Abstract)

Sebastian Siatkowski , University of California, Santa Barbara
Chuanhe Jay Shan , University of California, Santa Barbara
Li-C. Wang , University of California, Santa Barbara
Nikolas Sumikawat , Freescale Semiconductor, Inc.
W. Robert Daasch , Portland State University
John M. Carulli , GlobalFoundries
pp. 1-6

Predicting Vt mean and variance from parallel Id measurement with model-fitting technique (Abstract)

Chih-Ying Tsai , Dept. of Electronics Engineering & Institute of Electronics, National Chiao Tung University, Hsinchu, Taiwan
Kao-Chi Lee , Dept. of Electronics Engineering & Institute of Electronics, National Chiao Tung University, Hsinchu, Taiwan
Chien-Hsueh Lin , Dept. of Electronics Engineering & Institute of Electronics, National Chiao Tung University, Hsinchu, Taiwan
Sung-Chu Yu , United Microelectronics Corporation, Taiwan
Wen-Rong Liau , United Microelectronics Corporation, Taiwan
Alex Chun-Liang Hou , United Microelectronics Corporation, Taiwan
Ying-Yen Chen , Realtek Semiconductor Corporation, Taiwan
Chun-Yi Kuo , Realtek Semiconductor Corporation, Taiwan
Jih-Nung Lee , Realtek Semiconductor Corporation, Taiwan
Mango C.-T. Chao , Dept. of Electronics Engineering & Institute of Electronics, National Chiao Tung University, Hsinchu, Taiwan
pp. 1-6

Yield improvement of an EEPROM for automotive applications while maintaining high reliability (Abstract)

Gregor Schatzberger , ams AG, Premstaetten, Austria
Friedrich Peter Leisenberger , ams AG, Premstaetten, Austria
Peter Sarson , ams AG, Premstaetten, Austria
pp. 1-6

Active polymers for bio medical microdevices and microfluidic systems (Abstract)

Bonnie Lynne Gray , Microinstrumentation Lab, School of Engineering Science, Simon Fraser University, Burnaby, BC
pp. 1

Building trust in 3PIP using asset-based security property verification (Abstract)

Juan Portillo , Department of Electrical and Computer Engineering, University of Texas at San Antonio, San Antonio, TX, USA
Eugene John , Department of Electrical and Computer Engineering, University of Texas at San Antonio, San Antonio, TX, USA
Seetharam Narasimhan , Security Center of Excellence, Intel Corporation, Hillsboro, OR, USA
pp. 1-6

Revealing SRAM memory content using spontaneous photon emission (Abstract)

Franco Stellari , IBM Watson Research Center - 1101 Kitchawan Rd, Yorktown Height, NY, 10598, USA - 914-945-3223
Peilin Song , IBM Watson Research Center - 1101 Kitchawan Rd, Yorktown Height, NY, 10598, USA - 914-945-3223
Manuel Villalobos , IBM System and Technology Group - 2070 Rt 52, Hopewell Junction, NY 1253, USA
John Sylvestri , IBM System and Technology Group - 2070 Rt 52, Hopewell Junction, NY 1253, USA
pp. 1-6

Test and diagnosis of paper-based microfluidic biochips (Abstract)

Jain-De Li , Department of Computer Science and Engineering, National Chung-Hsing University
Sying-Jyan Wang , Department of Computer Science and Engineering, National Chung-Hsing University
Katherine Shu-Min Li , Department of Computer Science and Engineering, National Sun Yat-Sen University
Tsung-Yi Ho , Department of Computer Science, National Tsing Hua University
pp. 1-6

Code-modulated embedded test for phased arrays (Abstract)

Kevin Greene , Department of Electrical and Computer Engineering, North Carolina State University, Raleigh, NC 27695
Vikas Chauhan , Department of Electrical and Computer Engineering, North Carolina State University, Raleigh, NC 27695
Brian Floyd , Department of Electrical and Computer Engineering, North Carolina State University, Raleigh, NC 27695
pp. 1-4

Post fabrication tuning of GaN based RF power amplifiers for pico-cell applications (Abstract)

Muhammad Ruhul Hasin , School of Electrical, Computer, and Energy Engineering, Arizona State University
Jennifer Kitchen , School of Electrical, Computer, and Energy Engineering, Arizona State University
pp. 1-4

Performance enhancement techniques and verification methods for radio frequency circuits and systems (Abstract)

Hari Chauhan , Dept. of Electrical and Computer Engineering, Northeastern University, Boston, MA 02115, USA
Marvin Onabajo , Dept. of Electrical and Computer Engineering, Northeastern University, Boston, MA 02115, USA
pp. 1-4

Session 4B — Panel data analytics in semiconductor manufacturing (Abstract)

Suriyaprakash Natarajan , Intel Corporation, John Carulli, GlobalFoundries
Li-C Wang , University of California, Santa Barbara
pp. 1

Thermal issues in test: An overview of the significant aspects and industrial practice (Abstract)

J. Alt , INTEL Germany
P. Bernardi , Politecnico di Torino Italy
A. Bosio , LIRMM France
R. Cantoro , Politecnico di Torino Italy
H. Kerkhoff , University of Twente The Netherland
A. Leininger , INTEL Germany
W. Molzer , INTEL Germany
A. Motta , STMicroelectronics, Italy
C. Pacha , INTEL Germany
A. Pagani , STMicroelectronics, Italy
A. Rohani , University of Twente The Netherland
R. Strasser , INTEL Germany
pp. 1-4

Effective generation and evaluation of diagnostic SBST programs (Abstract)

Andreas Riefert , Albert-Ludwigs-Universitat Freiburg, Georges-Köhler-Allee 051, 79110 Freiburg, Germany
Riccardo Cantoro , Politecnico di Torino, Corso Duca degli Abruzzi 24, 10129 Torino, Italy
Matthias Sauer , Albert-Ludwigs-Universitat Freiburg, Georges-Köhler-Allee 051, 79110 Freiburg, Germany
Matteo Sonza Reorda , Politecnico di Torino, Corso Duca degli Abruzzi 24, 10129 Torino, Italy
Bernd Becker , Albert-Ludwigs-Universitat Freiburg, Georges-Köhler-Allee 051, 79110 Freiburg, Germany
pp. 1-6

Reduction of diagnostic fail data volume and tester time using a dynamic N-cover algorithm (Abstract)

Shraddha Bodhe , Department of Electrical and Computer Engineering, Purdue University, West Lafayette, Indiana, USA
M. Enamul Amyeen , Intel Corporation, Hillsboro, Oregon, USA
Clariza Galendez , Intel Corporation, Hillsboro, Oregon, USA
Houston Mooers , Intel Corporation, Hillsboro, Oregon, USA
Irith Pomeranz , Department of Electrical and Computer Engineering, Purdue University, West Lafayette, Indiana, USA
Srikanth Venkataraman , Intel Corporation, Hillsboro, Oregon, USA
pp. 1-6

Using hardware testing approaches to improve software testing: Undetectable mutant identification (Abstract)

Jianwei Zhang , Ming Hsieh Department of Electrical Engineering, University of Southern California, Los Angeles, USA
Sandeep K. Gupta , Ming Hsieh Department of Electrical Engineering, University of Southern California, Los Angeles, USA
pp. 1-6

Accurate spectral testing with non-coherent sampling for large distortion to noise ratios (Abstract)

Yuming Zhuang , Department of Electrical and Computer Engineering, Iowa State University, Ames, IA, USA
Degang Chen , Department of Electrical and Computer Engineering, Iowa State University, Ames, IA, USA
pp. 1-6

Adaptive testing of analog/RF circuits using hardware extracted FSM models (Abstract)

Sabyasachi Deyati , Electrical & Computer Engineering, Georgia Institute of Technology, Atlanta Georgia 30332 USA
Barry J. Muldrey , Electrical & Computer Engineering, Georgia Institute of Technology, Atlanta Georgia 30332 USA
Abhijit Chatterjee , Electrical & Computer Engineering, Georgia Institute of Technology, Atlanta Georgia 30332 USA
pp. 1-6

Process independent gain measurement with low overhead via BIST/DUT co-design (Abstract)

Jae Woong Jeong , School of Electrical, Computer, and Energy Engineering, Arizona State University, Tempe, AZ
Jennifer Kitchen , School of Electrical, Computer, and Energy Engineering, Arizona State University, Tempe, AZ
Sule Ozev , School of Electrical, Computer, and Energy Engineering, Arizona State University, Tempe, AZ
pp. 1-6

Process variation oriented delay testing of SRAMs (Abstract)

Xuan Zuo , Electrical Engineering Department, University of Southern California, Los Angeles, CA, USA
Sandeep K. Gupta , Electrical Engineering Department, University of Southern California, Los Angeles, CA, USA
pp. 1-6

Security validation in IoT space (Abstract)

Sandip Ray , Strategic CAD Labs, Intel Corporation
Swarup Bhunia , Electrical and Computer Engineering Department, University of Florida
Yier Jin , Electrical and Computer Engineering Department, University of Central Florida
Mark Tehranipoor , Electrical and Computer Engineering Department, University of Florida
pp. 1

A programmable method for low-power scan shift in SoC integrated circuits (Abstract)

Ran Wang , ECE Dept., Duke University, Durham, NC
Bonita Bhaskaran , NVIDIA Inc. Santa Clara, CA
Karthikeyan Natarajan , NVIDIA Inc. Santa Clara, CA
Ayub Abdollahian , NVIDIA Inc. Santa Clara, CA
Kaushik Narayanun , NVIDIA Inc. Santa Clara, CA
Krishnendu Chakrabarty , ECE Dept., Duke University, Durham, NC
Amit Sanghani , NVIDIA Inc. Santa Clara, CA
pp. 1-6

Dynamic docking architecture for concurrent testing and peak power reduction (Abstract)

Milind Sonawane , DFT Engineering, NVIDIA Corp., 2701 San Thomas Expressway, Santa Clara, CA 95050, USA
Pavan Kumar Datla Jagannadha , DFT Engineering, NVIDIA Corp., 2701 San Thomas Expressway, Santa Clara, CA 95050, USA
Sailendra Chadalavada , DFT Engineering, NVIDIA Corp., 2701 San Thomas Expressway, Santa Clara, CA 95050, USA
Shantanu Sarangi , DFT Engineering, NVIDIA Corp., 2701 San Thomas Expressway, Santa Clara, CA 95050, USA
Mahmut Yilmaz , DFT Engineering, NVIDIA Corp., 2701 San Thomas Expressway, Santa Clara, CA 95050, USA
Amit Sanghani , DFT Engineering, NVIDIA Corp., 2701 San Thomas Expressway, Santa Clara, CA 95050, USA
Kathikeyan Natarajan , DFT Engineering, NVIDIA Corp., 2701 San Thomas Expressway, Santa Clara, CA 95050, USA
Jonathon E. Colburn , DFT Engineering, NVIDIA Corp., 2701 San Thomas Expressway, Santa Clara, CA 95050, USA
Anubhav Sinha , DFT Engineering, NVIDIA Corp., 2701 San Thomas Expressway, Santa Clara, CA 95050, USA
pp. 1-6

Impact of crosstalk and process variation on capture power reduction for at-speed test (Abstract)

Surya Piplani , Indian Institute of Technology, Delhi, India, STMicroelectronics Pvt. Ltd., Greater Noida, India
G. S. Visweswaran , Indraprastha Institute of Information, Technology, Delhi, India
Anshul Kumar , Indian Institute of Technology, Delhi, India
pp. 1-6

Security primitives (PUF and TRNG) with STT-MRAM (Abstract)

Elena Ioana Vatajelu , Politecnico di Torino, Dipartimento di Automatica e Informatica, Turin, Italy
Giorgio Di Natale , LIRMM (Université de Montpellier /CNRS UMR 5506), Montpellier, France
Paolo Prinetto , Politecnico di Torino, Dipartimento di Automatica e Informatica, Turin, Italy
pp. 1-4

Security of emerging non-volatile memories: Attacks and defenses (Abstract)

Kaveh Shamsi , Department of Electrical and Computer Engineering, University of Central Florida
Yier Jin , Department of Electrical and Computer Engineering, University of Central Florida
pp. 1-4

Thwarting timing attacks on NEMS relay based designs (Abstract)

Bodhisatwa Mazumdar , New York University Abu Dhabi
Samah Mohamed Saeed , University of Washington, Tacoma
Sk Subidh Ali , New York University Abu Dhabi
Ozgur Sinanoglu , New York University Abu Dhabi
pp. 1-4

Test implications and challenges in near threshold computing special session (Abstract)

Mehdi Tahoori , Faculty of Informatics, Karlsruhe Institute of Technology, Karlsruhe, Germany
Rob Aitken , ARM Inc., San Jose, USA
Sriram R. Vangal , Intel Corporation, Hillsboro, OR, USA
Bal Sandhu , ARM Inc., San Jose, CA, USA
pp. 1

Accurate linearity testing with impure sinusoidal stimulus robust against flicker noise (Abstract)

Yuming Zhuang , Department of Electrical and Computer Engineering, Iowa State University, Ames, IA, USA
Tao Chen , Department of Electrical and Computer Engineering, Iowa State University, Ames, IA, USA
Shravan Chaganti , Department of Electrical and Computer Engineering, Iowa State University, Ames, IA, USA
Degang Chen , Department of Electrical and Computer Engineering, Iowa State University, Ames, IA, USA
pp. 1-6

On-die learning-based self-calibration of analog/RF ICs (Abstract)

Georgios Volanis , Department of Electrical Engineering, The University of Texas at Dallas, Richardson, TX 75080
Dzmitry Maliuk , Department of Electrical Engineering, Yale University, New Haven, CT 06520
Yichuan Lu , Department of Electrical Engineering, The University of Texas at Dallas, Richardson, TX 75080
Kiruba S. Subramani , Department of Electrical Engineering, The University of Texas at Dallas, Richardson, TX 75080
Angelos Antonopoulos , Department of Electrical Engineering, The University of Texas at Dallas, Richardson, TX 75080
Yiorgos Makris , Department of Electrical Engineering, The University of Texas at Dallas, Richardson, TX 75080
pp. 1-6

Real-time DC motor error detection and control compensation using linear checksums (Abstract)

Md Imran Momtaz , Electrical and Computer Engineering, Georgia Institute of Technology, Atlanta GA 30332
Suvadeep Banerjee , Electrical and Computer Engineering, Georgia Institute of Technology, Atlanta GA 30332
Abhijit Chatterjee , Electrical and Computer Engineering, Georgia Institute of Technology, Atlanta GA 30332
pp. 1-6

Cache- and register-aware system reliability evaluation based on data lifetime analysis (Abstract)

Maha Kooli , Laboratoire d'Informatique, de Robotique et de Microelectronique de Montpellier (LIRMM), France
Firas Kaddachi , Laboratoire d'Informatique, de Robotique et de Microelectronique de Montpellier (LIRMM), France
Giorgio Di Natale , Laboratoire d'Informatique, de Robotique et de Microelectronique de Montpellier (LIRMM), France
Alberto Bosio , Laboratoire d'Informatique, de Robotique et de Microelectronique de Montpellier (LIRMM), France
pp. 1-6

Microprocessor reliability-performance tradeoffs assessment at the microarchitecture level (Abstract)

Sotiris Tselonis , Department of Informatics & Telecommunications, University of Athens, Greece
Manolis Kaliorakis , Department of Informatics & Telecommunications, University of Athens, Greece
Nikos Foutris , Department of Informatics & Telecommunications, University of Athens, Greece
George Papadimitriou , Department of Informatics & Telecommunications, University of Athens, Greece
Dimitris Gizopoulos , Department of Informatics & Telecommunications, University of Athens, Greece
pp. 1-6

Online soft-error vulnerability estimation for memory arrays (Abstract)

Arunkumar Vijayan , Karlsruhe Institute of Technology, Germany
Abhishek Koneru , Department of Electrical and Computer Engineering, Duke University, Durham, NC, USA
Mojtaba Ebrahimit , Karlsruhe Institute of Technology, Germany
Krishnendu Chakrabarty , Department of Electrical and Computer Engineering, Duke University, Durham, NC, USA
Mehdi B. Tahoori , Karlsruhe Institute of Technology, Germany
pp. 1-6

ECC-ASPIRIN: An ECC-assisted post-package repair scheme for aging errors in DRAMs (Abstract)

Dae-Hyun Kim , Georgia Institute of Technology, Atlanta, GA 30332, USA
Linda S. Milor , Georgia Institute of Technology, Atlanta, GA 30332, USA
pp. 1-6

Fault modeling and testing of resistive nonvolatile-8T SRAMs (Abstract)

Yu-Ting Li , Department of Electrical Engineering, National Central University, Taoyuan, Taiwan 320
Yong-Xiao Chen , Department of Electrical Engineering, National Central University, Taoyuan, Taiwan 320
Jin-Fu Li , Department of Electrical Engineering, National Central University, Taoyuan, Taiwan 320
pp. 1-6

SRAM yield-per-area optimization under spatially-correlated process variation (Abstract)

Jizhe Zhang , Ming Hsieh Department of Electrical Engineering, University of Southern California, Los Angeles, CA 90089-2562
Sandeep K. Gupta , Ming Hsieh Department of Electrical Engineering, University of Southern California, Los Angeles, CA 90089-2562
pp. 1-6

Introduction to approximate computing (Abstract)

Jie Han , Department of Electrical and Computer Engineering, University of Alberta, Edmonton, Alberta, Canada
pp. 1

Fault tolerant approximate computing using emerging non-volatile spintronic memories (Abstract)

Fabian Oboril , Karlsruhe Institute of Technology (KIT), Germany
Azadeh Shirvanian , Karlsruhe Institute of Technology (KIT), Germany
Mehdi Tahoori , Karlsruhe Institute of Technology (KIT), Germany
pp. 1

Fault tolerance of approximate compute algorithms (Abstract)

Hans-Joachim Wunderlich , Institute of Computer Architecture and Computer Engineering, University of Stuttgart Pfaffenwaldring 47, D-70569, Germany
Claus Braun , Institute of Computer Architecture and Computer Engineering, University of Stuttgart Pfaffenwaldring 47, D-70569, Germany
Alexander Scholl , Institute of Computer Architecture and Computer Engineering, University of Stuttgart Pfaffenwaldring 47, D-70569, Germany
pp. 1

Flexible scan interface architecture for complex SoCs (Abstract)

Milind Sonawane , DFT Engineering, NVIDIA Corp, 2701 San Tomas Expressway, Santa Clara, CA 95050, USA
Sailendra Chadalavada , DFT Engineering, NVIDIA Corp, 2701 San Tomas Expressway, Santa Clara, CA 95050, USA
Shantanu Sarangi , DFT Engineering, NVIDIA Corp, 2701 San Tomas Expressway, Santa Clara, CA 95050, USA
Amit Sanghani , DFT Engineering, NVIDIA Corp, 2701 San Tomas Expressway, Santa Clara, CA 95050, USA
Mahmut Yilmaz , DFT Engineering, NVIDIA Corp, 2701 San Tomas Expressway, Santa Clara, CA 95050, USA
Pavan Kumar Datla Jagannadha , DFT Engineering, NVIDIA Corp, 2701 San Tomas Expressway, Santa Clara, CA 95050, USA
Jonathon E. Colburn , DFT Engineering, NVIDIA Corp, 2701 San Tomas Expressway, Santa Clara, CA 95050, USA
pp. 1-6

Optimization of the IEEE 1687 access network for hybrid access schedules (Abstract)

Srinivasa Shashank Nuthakki , Department of Electronics and Electrical Communication Engineering, Indian Institute of Technology, Kharagpur, India
Rajit Karmakar , Department of Electronics and Electrical Communication Engineering, Indian Institute of Technology, Kharagpur, India
Santanu Chattopadhyay , Department of Electronics and Electrical Communication Engineering, Indian Institute of Technology, Kharagpur, India
Krishnendu Chakrabarty , Department of Electrical and Computer Engineering, Duke University, Durham, NC, USA
pp. 1-6

Test method and scheme for low-power validation in modern SOC integrated circuits (Abstract)

Bonita Bhaskaran , NVIDIA Corporation, Santa Clara, CA
Amit Sanghani , NVIDIA Corporation, Santa Clara, CA
Kaushik Narayanun , NVIDIA Corporation, Santa Clara, CA
Ayub Abdollahian , NVIDIA Corporation, Santa Clara, CA
Amit Laknaur , NVIDIA Corporation, Santa Clara, CA
pp. 1-6

Special panel session IIB: "System validation and silicon debug — Is standardization possible?" (Abstract)

Mike Ricchetti , Synopsys, USA
Eric Rentschler , Mentor Graphics, USA
Amit Majumdar , Xilinx, USA
Mike Lowe , Samsung, USA
Mark LaVine , ARM, USA
Skip Lindsey , Intel, USA
Sharad Kumar , NXP, India
pp. 1

Faults in data prefetchers: Performance degradation and variability (Abstract)

Nikos Foutris , Department of Informatics & Telecommunications, University of Athens, Athens, Greece
Athanasios Chatzidimitriou , Department of Informatics & Telecommunications, University of Athens, Athens, Greece
Dimitris Gizopoulos , Department of Informatics & Telecommunications, University of Athens, Athens, Greece
John Kalamatianos , AMD Research, RAS Architecture, Advanced Micro Devices, Inc., Boxborough, MA, USA
Vilas Sridharan , AMD Research, RAS Architecture, Advanced Micro Devices, Inc., Boxborough, MA, USA
pp. 1-6

Scalable parallel fault simulation for shared-memory multiprocessor systems (Abstract)

Stavros Hadjitheophanous , University of Cyprus, Cyprus, KIOS Research Center
Stelios N. Neophytou , University of Nicosia, Cyprus, KIOS Research Center
Maria K. Michael , University of Cyprus, Cyprus, KIOS Research Center
pp. 1-6

Test-point insertion efficiency analysis for LBIST applications (Abstract)

Miao Tony He , Department of Electrical and Computer Engineering, University of Florida, Gainesville, FL 32611
Gustavo K. Contreras , Department of Electrical and Computer Engineering, University of Florida, Gainesville, FL 32611
Mark Tehranipoor , Department of Electrical and Computer Engineering, University of Florida, Gainesville, FL 32611
Dat Tran , NXP Semiconductors, Austin, Texas 78735
LeRoy Winemberg , NXP Semiconductors, Austin, Texas 78735
pp. 1-6

Lifetime reliability modeling and estimation in multi-core systems (Abstract)

Antonio Miele , Dip. Elettronica, Informazione e Bioingegneria - Politecnico di Milano, Italy
pp. 1

Early system failure prediction by using aging in situ monitors: Methodology of implementation and application results (Abstract)

Lorena Anghel , Grenoble-Alps University, TIMA Laboratory, Grenoble, France
A. Benhassain , ST Microelectronics Crolles, France
A. Sivadasan , ST Microelectronics Crolles, France
F. Cacho , ST Microelectronics Crolles, France
V. Huard , ST Microelectronics Crolles, France
pp. 1

Runtime resource management for lifetime extension in multi-core systems (Abstract)

Cristiana Boichini , Dip. Elettronica, Informazione e Bioingegneria - Politecnico di Milano, Italy
pp. 1
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