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2015 IEEE 33rd VLSI Test Symposium (VTS) (2015)
Napa, CA, USA
April 27, 2015 to April 29, 2015
ISBN: 978-1-4799-7597-6
TABLE OF CONTENTS

[Title page] (PDF)

pp. 1

[Blank page] (PDF)

pp. 1

[Title page] (PDF)

pp. 1

Foreword (PDF)

Claude Thibeault , E. Tech. Sup. Montreal, CA, USA
pp. 1

Acknowledgments (PDF)

Claude Thibeault , E. Tech. Sup. Montreal, CA, USA
pp. 1

Fault diagnosis for flow-based microfluidic biochips (Abstract)

Kai Hu , Department of Electrical & Computer Engineering, Duke University, Durham, NC, 27708, USA
Bhargab B. Bhattacharya , Advanced Computing & Microelectronics Unit, Indian Statistical Institute, Kolkata-700108, India
Krishnendu Chakrabarty , Department of Electrical & Computer Engineering, Duke University, Durham, NC, 27708, USA
pp. 1-6

Rapid online fault recovery for cyber-physical digital microfluidic biochips (Abstract)

Christopher Jaress , Department of Computer Science and Engineering, University of California, Riverside, USA
Philip Brisk , Department of Computer Science and Engineering, University of California, Riverside, USA
Daniel Grissom , Department of Engineering and Computer Science, Azusa Pacific University, CA, USA
pp. 1-6

Fault modeling and testing of 1T1R memristor memories (Abstract)

Yong-Xiao Chen , Advanced Reliable Systems (ARES) Lab., Department of Electrical Engineering, National Central University, Taoyuan, Taiwan 320
Jin-Fu Li , Advanced Reliable Systems (ARES) Lab., Department of Electrical Engineering, National Central University, Taoyuan, Taiwan 320
pp. 1-6

A low cost jitter separation and characterization method (Abstract)

Li Xu , Department of Electrical and Computer Engineering, Iowa State University, Ames, USA
Yan Duan , Department of Electrical and Computer Engineering, Iowa State University, Ames, USA
Degang Chen , Department of Electrical and Computer Engineering, Iowa State University, Ames, USA
pp. 1-5

Ultrafast stimulus error removal algorithm for ADC linearity test (Abstract)

Tao Chen , Department of Electrical and Computer Engineering, Iowa State University, Ames, USA
Degang Chen , Department of Electrical and Computer Engineering, Iowa State University, Ames, USA
pp. 1-5

Disturbance-free BIST for loop characterization of DC-DC buck converters (Abstract)

Navankur Beohar , School of Electrical, Computer, and Energy Engineering, Arizona State University, Tempe, USA
Priyanka Bakliwal , School of Electrical, Computer, and Energy Engineering, Arizona State University, Tempe, USA
Sidhanto Roy , School of Electrical, Computer, and Energy Engineering, Arizona State University, Tempe, USA
Debashis Mandal , School of Electrical, Computer, and Energy Engineering, Arizona State University, Tempe, USA
Philippe Adell , NASA Jet Propulsion Laboratory, Pasadena, CA, USA
Bert Vermeire , Space Micro Inc. San Diego, CA, USA
Bertan Bakkaloglu , School of Electrical, Computer, and Energy Engineering, Arizona State University, Tempe, USA
Sule Ozev , School of Electrical, Computer, and Energy Engineering, Arizona State University, Tempe, USA
pp. 1-6

A multi-layered methodology for defect-tolerance of datapath modules in processors (Abstract)

Hsunwei Hsiung , Ming Hsieh Department of Electrical Engineering, University of Southern California, Los Angeles, 90089-2562, USA
Sandeep K. Gupta , Ming Hsieh Department of Electrical Engineering, University of Southern California, Los Angeles, 90089-2562, USA
pp. 1-6

PPB: Partially-working processors binning for maximizing wafer utilization (Abstract)

Da Cheng , Xilinx, inc., 2100 Logic Drive, San Jose, CA, USA
Sandeep K. Gupta , Department of Electrical Engineering, University of Southern California, Los Angeles, USA
pp. 1-6

In-depth soft error vulnerability analysis using synthetic benchmarks (Abstract)

Shahrzad Mirkhani , Computer Engineering Research Center, The University of Texas at Austin, USA
Balavinayagam Samynathan , Computer Engineering Research Center, The University of Texas at Austin, USA
Jacob A. Abraham , Computer Engineering Research Center, The University of Texas at Austin, USA
pp. 1-6

TMO: A new class of attack on cipher misusing test infrastructure (Abstract)

Sk Subidh Ali , New York University Abu Dhabi (NYUAD), United Arab Emirates
Ozgur Sinanoglu , New York University Abu Dhabi (NYUAD), United Arab Emirates
pp. 1-4

A call to action: Securing IEEE 1687 and the need for an IEEE test Security Standard (Abstract)

Jennifer Dworak , Department of Computer Science & Engineering, Southern Methodist University, Dallas, Texas, USA
Al Crouch , ASSET InterTech, Inc., Richardson, Texas, USA
pp. 1-4

Enabling unauthorized RF transmission below noise floor with no detectable impact on primary communication performance (Abstract)

Doohwang Chang , School of Electrical, Computer, and Energy Engineering, Arizona State University, USA
Bertan Bakkaloglu , School of Electrical, Computer, and Energy Engineering, Arizona State University, USA
Sule Ozev , School of Electrical, Computer, and Energy Engineering, Arizona State University, USA
pp. 1-4

Extracting effective functional tests from commercial programs (Abstract)

Sreekumar Vadakke Kodakara , Intel® Corporation, USA
Mehul V. Sagar , Intel® Corporation, USA
Joel Yuen , Intel® Corporation, USA
pp. 1-6

Statistical techniques for predicting system-level failure using stress-test data (Abstract)

Harry H. Chen , MediaTek Inc, Hsinchu, Taiwan
Shih-Hua Kuo , MediaTek Inc, Hsinchu, Taiwan
Jonathan Tung , MediaTek Inc, Hsinchu, Taiwan
Mango C.-T. Chao , Dept. of Electronics Engineering & Institute of Electronics, National Chiao Tung University, Hsinchu, Taiwan
pp. 1-6

Yield prognosis for fab-to-fab product migration (Abstract)

Ali Ahmadi , Department of Electrical Engineering, The University of Texas at Dallas, Richardson, 75080, USA
Ke Huang , Department of Electrical and Computer Engineering, San Diego State University, CA 92115, USA
Amit Nahar , Texas Instruments Inc., 12500 TI Boulevard, MS 8741, Dallas, 75243, USA
Bob Orr , Texas Instruments Inc., 12500 TI Boulevard, MS 8741, Dallas, 75243, USA
Michael Pas , Texas Instruments Inc., 12500 TI Boulevard, MS 8741, Dallas, 75243, USA
John M. Carulli , GlobalFoundries, 400 Stone Break Road Extension, Malta, NY 12020, USA
Yiorgos Makris , Department of Electrical Engineering, The University of Texas at Dallas, Richardson, 75080, USA
pp. 1-6

3D microelectronic with BEOL compatible devices (Abstract)

D Drouin , Laboratoire Nanotechnologies Nanosystemes (LN2) - CNRS UMI-3463, Universite de Sherbrooke, Canada
M A-Bounouar , Institut Interdisciplinaire d'Innovation Technologique (3IT), Universite de Sherbrooke, 3000 Boul. Universite, J1K OA5, Quebec, Canada
G Droulers , Laboratoire Nanotechnologies Nanosystemes (LN2) - CNRS UMI-3463, Universite de Sherbrooke, Canada
M Labalette , Laboratoire Nanotechnologies Nanosystemes (LN2) - CNRS UMI-3463, Universite de Sherbrooke, Canada
M Pioro-Ladriere , Departement de physique, Universite de Sherbrooke, 2500 Boul. Universite, J1K 2R1, Quebec, Canada
A Souifi , Institut des Nanotechnologies de Lyon - UMR CNRS 5270, 7 av. Jean Capelle, 69621 Villeurbanne cedex, France
S Ecoffey , Laboratoire Nanotechnologies Nanosystemes (LN2) - CNRS UMI-3463, Universite de Sherbrooke, Canada
pp. 1

Special session: Hot topics: Statistical test methods (Abstract)

Manuel J. Barragan , TIMA, CNRS-Univeristé Grenoble-Alpes, France
Gildas Leger , IMSE-CNM, CSIC-Universidad de Sevilla, Spain
Florence Azais , LIRMM, CNRS-Université Montpellier 2, France
R. D. Blanton , Carnegie Mellon University, USA
Adit D. Singh , Auburn University, USA
Stephen Sunter , Mentor Graphics, Canada
pp. 1-2

ExTest scheduling for 2.5D system-on-chip integrated circuits (Abstract)

Ran Wang , ECE Dept., Duke University, Durham, NC, USA
Guoliang Li , AMD Inc. Shanghai, China
Rui Li , AMD Inc. Shanghai, China
Jun Qian , AMD Inc. Shanghai, China
Krishnendu Chakrabarty , ECE Dept., Duke University, Durham, NC, USA
pp. 1-6

Pulse shrinkage based pre-bond through silicon vias test in 3D IC (Abstract)

Chang Hao , School of Computer and Information, Hefei University of Technology, No.193, Tunxi Road, Anhui, China, 230009
Liang Huaguo , School of Electronic Science & Applied Physics, Hefei University of Technology, No.193, Tunxi Road, Anhui, China, 230009
pp. 1-6

Testing of 3D-stacked ICs with hard- and soft-dies - a Particle Swarm Optimization based approach (Abstract)

Rajit Karmakar , Dept. of Electronics & Electrical Comm. Engineering, Indian Institute of Technology Kharagpur, India, 721302
Aditya Agarwal , Dept. of Electronics & Electrical Comm. Engineering, Indian Institute of Technology Kharagpur, India, 721302
Santanu Chattopadhyay , Dept. of Electronics & Electrical Comm. Engineering, Indian Institute of Technology Kharagpur, India, 721302
pp. 1-6

Improving diagnosis resolution of a fault detection test set (Abstract)

Andreas Riefert , Albert-Ludwigs-Universität Freiburg, Georges-Köhler-Allee 051, 79110, Germany
Matthias Sauer , Albert-Ludwigs-Universität Freiburg, Georges-Köhler-Allee 051, 79110, Germany
Sudhakar Reddy , University of Iowa, 5324 Seamans Center, United States
Bernd Becker , Albert-Ludwigs-Universität Freiburg, Georges-Köhler-Allee 051, 79110, Germany
pp. 1-6

Improving the accuracy of defect diagnosis by considering reduced diagnostic information (Abstract)

Irith Pomeranz , School of Electrical & Computer Eng., Purdue University, W. Lafayette, IN 47907, U.S.A.
pp. 1-6

Signature oriented model pruning to facilitate multi-threaded processors debugging (Abstract)

Fatemeh Refan , School of Electrical and Computer Engineering, College of Engineering, University of Tehran, Iran
Bijan Alizadeh , School of Electrical and Computer Engineering, College of Engineering, University of Tehran, Iran
Zainalabedin Navabi , School of Electrical and Computer Engineering, College of Engineering, University of Tehran, Iran
pp. 1-6

At-Product-Test Dedicated Adaptive supply-resonance suppression (Abstract)

Kohki Taniguchi , Graduate School of System Informatics, Kobe University, Japan
Noriyuki Miura , Graduate School of System Informatics, Kobe University, Japan
Taisuke Hayashi , Graduate School of System Informatics, Kobe University, Japan
Makoto Nagata , Graduate School of System Informatics, Kobe University, Japan
pp. 1-6

Low cost high frequency signal synthesis: Application to RF channel interference testing (Abstract)

Xian Wang , School of Electrical and Computer Engineering, Georgia Institute of Technology, Atlanta, USA
Debashis Banerjee , School of Electrical and Computer Engineering, Georgia Institute of Technology, Atlanta, USA
Abhijit Chatterjee , School of Electrical and Computer Engineering, Georgia Institute of Technology, Atlanta, USA
pp. 1-6

Automated testing of mixed-signal integrated circuits by topology modification (Abstract)

Anthony Coyette , Department of Electrical Engineering, KU Leuven, Kasteelpark Arenberg 10, 3001, Belgium
Baris Esen , Department of Electrical Engineering, KU Leuven, Kasteelpark Arenberg 10, 3001, Belgium
Ronny Vanhooren , ON Semiconductor Belgium
Wim Dobbelaere , ON Semiconductor Belgium
Georges Gielen , Department of Electrical Engineering, KU Leuven, Kasteelpark Arenberg 10, 3001, Belgium
pp. 1-6

Impact of parameter variations on FinFET faults (Abstract)

G. Harutyunyan , Synopsys, USA
G. Tshagharyan , Synopsys, USA
Y. Zorian , Synopsys, USA
pp. 1-4

Memory repair for high defect densities (Abstract)

Michael Nicolaidis , TIMA (CNRS, Grenoble INP, UJF), France
Panagiota Papavramidou , TIMA (CNRS, Grenoble INP, UJF), France
pp. 1-4

Horizontal-FPN fault coverage improvement in production test of CMOS imagers (Abstract)

R. Fei , Université Grenoble Alpes, TIMA, F-38000, France
J. Moreau , STMicroelectronics, 12 rue Jules Horowitz, F-38000 Grenoble, France
S. Mir , CNRS, TIMA, F-38000 Grenoble, France
A. Marcellin , STMicroelectronics, 12 rue Jules Horowitz, F-38000 Grenoble, France
C. Mandier , STMicroelectronics, 12 rue Jules Horowitz, F-38000 Grenoble, France
E. Huss , STMicroelectronics, 12 rue Jules Horowitz, F-38000 Grenoble, France
G. Palmigiani , STMicroelectronics, 12 rue Jules Horowitz, F-38000 Grenoble, France
P. Vitrou , STMicroelectronics, 12 rue Jules Horowitz, F-38000 Grenoble, France
T. Droniou , STMicroelectronics, 12 rue Jules Horowitz, F-38000 Grenoble, France
pp. 1-6

Capacitive Coupling Mitigation for TSV-based 3D ICs (Abstract)

Ashkan Eghbal , Center for Pervasive Communications and Computing, Department of Electrical Engineering and Computer Science, University of California, Irvine, USA
Pooria M. Yaghini , Center for Pervasive Communications and Computing, Department of Electrical Engineering and Computer Science, University of California, Irvine, USA
Nader Bagherzadeh , Center for Pervasive Communications and Computing, Department of Electrical Engineering and Computer Science, University of California, Irvine, USA
pp. 1-6

Improving accuracy of on-chip diagnosis via incremental learning (Abstract)

Xuanle Ren , Department of Electrical and Computer Engineering, Carnegie Mellon University, 5000 Forbes Ave, Pittsburgh, PA, USA
Mitchell Martin , Department of Electrical and Computer Engineering, Carnegie Mellon University, 5000 Forbes Ave, Pittsburgh, PA, USA
R. D. Blanton , Department of Electrical and Computer Engineering, Carnegie Mellon University, 5000 Forbes Ave, Pittsburgh, PA, USA
pp. 1-6

Resiliency challenges in sub-10nm technologies (Abstract)

Rob Aitken , ARM, San Jose, CA, USA
Ethan H. Cannon , The Boeing Company, Seattle, WA, USA
Mondira Pant , Intel, Hudson, MA, USA
Mehdi B. Tahoori , Karlsruhe Institute of Technology, Germany
pp. 1-4

Panel: Analog/RF BIST: Are we there yet? (Abstract)

Sule Ozev , Arizona State University, USA
Linda Milor , Georgia Institute of Technology, USA
pp. 1

No Fault Found: The root cause (Abstract)

Erik Larsson , Lund University, Sweden
Bill Eklow , Cisco, California, USA
Scott Davidsson , Oracle, California, USA
Rob Aitken , ARM, California, USA
Artur Jutman , Testonica, Estonia
Christophe Lotz , Aster Tech., France
pp. 1

Special session 8C: E.J. McCluskey doctoral thesis award semi-final (Abstract)

M. Portolan , TIMA Laboratory, France
K. Huang , San Diego State University, USA
pp. 1-2

Abstraction-based relation mining for functional test generation (Abstract)

Kelson Gent , Bradley Department of Electrical and Computer Engineering, Virginia Tech, Blacksburg, 24061, USA
Michael S. Hsiao , Bradley Department of Electrical and Computer Engineering, Virginia Tech, Blacksburg, 24061, USA
pp. 1-6

Random pattern generation for post-silicon validation of DDR3 SDRAM (Abstract)

Hao-Yu Yang , Dept. of Electronics Engineering & Institute of Electronics, National Chiao Tung University, Hsinchu, Taiwan
Shih-Hua Kuo , Dept. of Electronics Engineering & Institute of Electronics, National Chiao Tung University, Hsinchu, Taiwan
Tzu-Hsuan Huang , Dept. of Electronics Engineering & Institute of Electronics, National Chiao Tung University, Hsinchu, Taiwan
Chi-Hung Chen , Winbond Electronics Corporation, Hsinchu, Taiwan
Chris Lin , Winbond Electronics Corporation, Hsinchu, Taiwan
Mango C.-T. Chao , Dept. of Electronics Engineering & Institute of Electronics, National Chiao Tung University, Hsinchu, Taiwan
pp. 1-6

UPF-based formal verification of low power techniques in modern processors (Abstract)

Reza Sharafinejad , School of Electrical and Computer Engineering, College of Engineering, University of Tehran, P.o.Box 14395-515, Iran
Bijan Alizadeh , School of Computer Science, Institute for Research in Fundamental Sciences (IPM), P.o.Box 19395-5746, Tehran, Iran
Masahiro Fujita , VLSI Design and Education Center, The University of Tokyo, P.o.Box 113-8654, Japan
pp. 1-6

MBIST and statistical hypothesis test for time dependent dielectric breakdowns due to GOBD vs. BTDDB in an SRAM array (Abstract)

Woongrae Kim , School of Electrical and Computer Engineering, Georgia Institute of Technology, Atlanta, USA
Chang-Chih Chen , School of Electrical and Computer Engineering, Georgia Institute of Technology, Atlanta, USA
Soonyoung Cha , School of Electrical and Computer Engineering, Georgia Institute of Technology, Atlanta, USA
Linda Milor , School of Electrical and Computer Engineering, Georgia Institute of Technology, Atlanta, USA
pp. 1-6

An early prediction methodology for aging sensor insertion to assure safe circuit operation due to NBTI aging (Abstract)

Andres Gomez , National Institute for Astrophysics, Optics and Electronics - INAOE, Mexico
Leticia Poehls , Catholic University of Rio Grande do Sul - PUCRS, Brazil
Fabian Vargas , Catholic University of Rio Grande do Sul - PUCRS, Brazil
Victor Champac , National Institute for Astrophysics, Optics and Electronics - INAOE, Mexico
pp. 1-6

Integral impact of BTI and voltage temperature variation on SRAM sense amplifier (Abstract)

Innocent Agbo , Delft University of Technology, Faculty of Electrical Engineering, Mathematics and CS, Mekelweg 4, 2628 CD, The Netherlands
Mottaqiallah Taouil , Delft University of Technology, Faculty of Electrical Engineering, Mathematics and CS, Mekelweg 4, 2628 CD, The Netherlands
Said Hamdioui , Delft University of Technology, Faculty of Electrical Engineering, Mathematics and CS, Mekelweg 4, 2628 CD, The Netherlands
Halil Kukner , IMEC vzw, Kapeldreef 75, 3001 Leuven, Belgium
Pieter Weckx , IMEC vzw, Kapeldreef 75, 3001 Leuven, Belgium
Praveen Raghavan , IMEC vzw, Kapeldreef 75, 3001 Leuven, Belgium
Francky Catthoor , IMEC vzw, Kapeldreef 75, 3001 Leuven, Belgium
pp. 1-6

A robust digital sensor IP and sensor insertion flow for in-situ path timing slack monitoring in SoCs (Abstract)

M. Sadi , Dept. of Electrical & Computer Engineering, University of Connecticut, Storrs, USA
L. Winemberg , Freescale Semiconductor, Austin, TX, USA
M. Tehranipoor , Dept. of Electrical & Computer Engineering, University of Connecticut, Storrs, USA
pp. 1-6

Scalability study of PSANDE: Power supply analysis for noise and delay estimation (Abstract)

Sushmita Kadiyala Rao , CSEE Department, University of Maryland, Baltimore County, USA
Bharath Shivashankar , CSEE Department, University of Maryland, Baltimore County, USA
Ryan Robucci , CSEE Department, University of Maryland, Baltimore County, USA
Nilanjan Banerjee , CSEE Department, University of Maryland, Baltimore County, USA
Chintan Patel , CSEE Department, University of Maryland, Baltimore County, USA
pp. 1-6

Robust counterfeit PCB detection exploiting intrinsic trace impedance variations (Abstract)

Fengchao Zhang , Department of Electrical Engineering and Computer Science, Case Western Reserve University, Cleveland, OH 44106, USA
Andrew Hennessy , Department of Electrical Engineering and Computer Science, Case Western Reserve University, Cleveland, OH 44106, USA
Swarup Bhunia , Department of Electrical Engineering and Computer Science, Case Western Reserve University, Cleveland, OH 44106, USA
pp. 1-6

Field, experimental, and analytical data on large-scale HPC systems and evaluation of the implications for exascale system design (Abstract)

Nathan DeBardeleben , Ultrascale Systems Research Center, Los Alamos National Laboratory, NM, USA
Sean Blanchard , Ultrascale Systems Research Center, Los Alamos National Laboratory, NM, USA
David Kaeli , Northeastern University, Boston, MA, USA
Paolo Rech , UFRGS, Porto Alegre, Brazil
pp. 1-2

Multi-cycle Circuit Parameter Independent ATPG for interconnect open defects (Abstract)

Dominik Erb , University of Freiburg, Germany
Karsten Scheibler , University of Freiburg, Germany
Matthias Sauer , University of Freiburg, Germany
Sudhakar M. Reddy , University of Iowa, USA
Bernd Becker , University of Freiburg, Germany
pp. 1-6

Test vector omission with minimal sets of simulated faults (Abstract)

Irith Pomeranz , School of Electrical and Computer Engineering, Purdue University, West Lafayette, IN 47907, U.S.A.
pp. 1-6

Test compaction by test cube merging for four-way bridging faults (Abstract)

Irith Pomeranz , School of Electrical and Computer Engineering, Purdue University, West Lafayette, IN 47907, U.S.A.
pp. 1-6

Testing cross wire opens within complex gates (Abstract)

Chao Han , Department of Electrical and Computer Engineering, Auburn University, AL, 36849, USA
Adit D. Singh , Department of Electrical and Computer Engineering, Auburn University, AL, 36849, USA
pp. 1-6

A definition of the number of detections for faults with single tests in a compact scan-based test set (Abstract)

Irith Pomeranz , School of Electrical and Computer Engineering, Purdue University, West Lafayette, IN 47907, U.S.A.
pp. 1-6

Efficient built-in self test of regular logic characterization vehicles (Abstract)

Ben Niewenhuis , Department of Electrical and Computer Engineering, Carnegie Mellon University, Pittsburgh, PA 15213, USA
R. D. Blanton , Department of Electrical and Computer Engineering, Carnegie Mellon University, Pittsburgh, PA 15213, USA
pp. 1-6
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