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2015 IEEE 33rd VLSI Test Symposium (VTS) (2015)
Napa, CA, USA
April 27, 2015 to April 29, 2015
ISBN: 978-1-4799-7597-6
pp: 1-6
Sushmita Kadiyala Rao , CSEE Department, University of Maryland, Baltimore County, USA
Bharath Shivashankar , CSEE Department, University of Maryland, Baltimore County, USA
Ryan Robucci , CSEE Department, University of Maryland, Baltimore County, USA
Nilanjan Banerjee , CSEE Department, University of Maryland, Baltimore County, USA
Chintan Patel , CSEE Department, University of Maryland, Baltimore County, USA
ABSTRACT
Variations in the power-distribution network are exacerbated because of scaled supply voltages and smaller noise margins in sub-nanometer designs, which adversely affect performance and yield. Power-Supply noise incurred by excessive simultaneous switching of multiple paths negatively impacts the timing of a circuit. Supply noise is a major issue especially during transition and delay test where test vectors cause increased switching as compared to functional operation resulting in increase in path delays. Test rejects due to excessive noise-induced failures during delay and transition testing negatively impacts yield. Hence there is a need to accurately characterize the resistive and inductive voltage drop caused by excessive switching. To our knowledge, inductive drop has been excluded to simplify noise analysis. In our previous work, we have presented a convolution-based dynamic method (herein referred to as PSANDE) to estimate both IR and Ldi/dt drop on small combinational and sequential circuits. In this paper we show that the effectiveness of the design partitioning technique makes the framework feasible for a larger design. Our dynamic approach involves selectively simulating only extracted switching logic which makes the run-time tractable as compared to prohibitive full-chip SPICE simulations. We also present data to show that PSANDE can accurately predict the power-supply noise due to clock tree switching. Data presented in this paper for power supply noise is based on a large ITC'99 sequential benchmark b17 circuit. with a maximum error of 8.2% in comparison to full-chip SPICE results.
INDEX TERMS
Transient analysis, Noise, Clocks, Switches, Power grids, Logic gates, Delays
CITATION

S. K. Rao, B. Shivashankar, R. Robucci, N. Banerjee and C. Patel, "Scalability study of PSANDE: Power supply analysis for noise and delay estimation," 2015 IEEE 33rd VLSI Test Symposium (VTS), Napa, CA, USA, 2015, pp. 1-6.
doi:10.1109/VTS.2015.7116293
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