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2014 IEEE 32nd VLSI Test Symposium (VTS) (2014)
Napa, CA, USA
April 13, 2014 to April 17, 2014
ISBN: 978-1-4799-2611-4
TABLE OF CONTENTS

[Blank page] (PDF)

pp. 1

[Title page] (PDF)

pp. 1

Foreword (PDF)

pp. 1

Fault simulation with test switching for static test compaction (Abstract)

Irith Pomeranz , School of Electrical and Computer Engineering Purdue University West Lafayette, IN 47907, U.S.A.
pp. 1-6

Fast evaluation of test vector sets using a simulation-based statistical metric (Abstract)

Shahrzad Mirkhani , Computer Engineering Research Center 201 E 24th Street, ACES Bldg., Austin, TX 78712 The University of Texas at Austin
Jacob A. Abraham , Computer Engineering Research Center 201 E 24th Street, ACES Bldg., Austin, TX 78712 The University of Texas at Austin
pp. 1-6

Improving CMOS open defect coverage using hazard activated tests (Abstract)

Chao Han , Department of Electrical and Computer Engineering Auburn University, Auburn AL, 36849
Adit D. Singh , Department of Electrical and Computer Engineering Auburn University, Auburn AL, 36849
pp. 1-6

Efficient Monte Carlo-based analog parametric fault modelling (Abstract)

Haralampos-G. Stratigopoulos , TIMA Laboratory (CNRS-Grenoble INP-UJF), 46 Av. Félix Viallet, 38031 Grenoble, France
Stephen Sunter , Mentor Graphics, 411 Legget Drive, Ottawa, Ontario K2K 3C9, Canada
pp. 1-6

A method for phase noise extraction from data communication (Abstract)

Allan Ecker , University of Washington Seattle, USA
Mani Soma , University of Washington Seattle, USA
pp. 1-6

Accurate and efficient method of jitter and noise separation and its application to ADC testing (Abstract)

Li Xu , Department of Electrical and Computer Engineering Iowa State University, Ames, IA, USA
Degang Chen , Department of Electrical and Computer Engineering Iowa State University, Ames, IA, USA
pp. 1-5

Testing methods for a write-assist disturbance-free dual-port SRAM (Abstract)

Hao-Yu Yang , Dept. of Electronics Engineering & Institute of Electronics, National Chiao Tung University, Hsinchu, Taiwan
Chen-Wei Lin , Dept. of Electronics Engineering & Institute of Electronics, National Chiao Tung University, Hsinchu, Taiwan
Chao-Ying Huang , Dept. of Electronics Engineering & Institute of Electronics, National Chiao Tung University, Hsinchu, Taiwan
Ching-Ho Lu , Dept. of Electronics Engineering & Institute of Electronics, National Chiao Tung University, Hsinchu, Taiwan
Chen-An Lai , Dept. of Electronics Engineering & Institute of Electronics, National Chiao Tung University, Hsinchu, Taiwan
Mango C.-T. Chao , Dept. of Electronics Engineering & Institute of Electronics, National Chiao Tung University, Hsinchu, Taiwan
Rei-Fu Huang , MediaTek Incorporation, Hsinchu, Taiwan
pp. 1-6

Built-in self test methodology for diagnosis of backend wearout mechanisms in SRAM cells (Abstract)

Woongrae Kim , School of Electrical and Computer Engineering, Georgia Institute of Technology, Atlanta, GA USA
Linda Milor , School of Electrical and Computer Engineering, Georgia Institute of Technology, Atlanta, GA USA
pp. 1-6

A built-in self-test technique for load inductance and lossless current sensing of DC-DC converters (Abstract)

Tao Liu , Arizona State University, Tempe, AZ 85287 USA
Chao Fu , Arizona State University, Tempe, AZ 85287 USA
Sule Ozev , Arizona State University, Tempe, AZ 85287 USA
Bertan Bakkaloglu , Arizona State University, Tempe, AZ 85287 USA
pp. 1-6

Alternative “safe” test of hysteretic power converters (Abstract)

X. Wang , Georgia Institute of Technology
K. Blanchard , Texas Instruments
S. Estella , Texas Instruments
A. Chatterjee , Georgia Institute of Technology
pp. 1-6

Accelerating capture of infrequent errors on ATE for silicon TV tuners (Abstract)

Y. Fan , Silicon Labs 400 West Cesar Chavez Austin, TX 78701 USA
A. Verma , Silicon Labs 400 West Cesar Chavez Austin, TX 78701 USA
D. S. Trager , Silicon Labs 400 West Cesar Chavez Austin, TX 78701 USA
R. K. Poorfard , Silicon Labs 400 West Cesar Chavez Austin, TX 78701 USA
J. Janney , Silicon Labs 400 West Cesar Chavez Austin, TX 78701 USA
S. Kumar , Silicon Labs 400 West Cesar Chavez Austin, TX 78701 USA
pp. 1-6

Self-heating thermal-aware testing of FPGAs (Abstract)

Abdulazim Amouri , Institute of Computer Engineering, Karlsruhe Institute of Technology (KIT), Karlsruhe, Germany
Jochen Hepp , Institute of Computer Engineering, Karlsruhe Institute of Technology (KIT), Karlsruhe, Germany
Mehdi Tahoori , Institute of Computer Engineering, Karlsruhe Institute of Technology (KIT), Karlsruhe, Germany
pp. 1-6

Structural Software-Based Self-Test of Network-on-Chip (Abstract)

Atefe Dalirsani , Institute of Computer Architecture and Computer Engineering, University of Stuttgart, Germany
Michael E. Imhof , Institute of Computer Architecture and Computer Engineering, University of Stuttgart, Germany
Hans-Joachim Wunderlich , Institute of Computer Architecture and Computer Engineering, University of Stuttgart, Germany
pp. 1-6

Accelerated online error detection in many-core microprocessor architectures (Abstract)

Manolis Kaliorakis , Dept. of Informatics & Telecomm., University of Athens, Greece
Mihalis Psarakis , Dept. of Informatics, University of Piraeus, Greece
Nikos Foutris , Dept. of Informatics & Telecomm., University of Athens, Greece
Dimitris Gizopoulos , Dept. of Informatics & Telecomm., University of Athens, Greece
pp. 1-6

Special session 4A: Elevator talks (PDF)

Jennifer Dworak , Southern Methodist University
pp. 1

Test generation and design-for-testability for flow-based mVLSI microfluidic biochips (Abstract)

Kai Hu , ECE Dept., Duke University, Durham, NC, USA
Tsung-Yi Ho , ECE Dept., Duke University, Durham, NC, USA
Krishnendu Chakrabarty , National Cheng Kung University, Tainan, Taiwan
pp. 1-6

Fault tolerant nanoarray circuits: Automatic design and verification (Abstract)

P. Ranone , Electronics and Telecommunication Department, Politecnico di Torino, Corso Duca degli Abruzzi 24, Italy
G. Turvani , Electronics and Telecommunication Department, Politecnico di Torino, Corso Duca degli Abruzzi 24, Italy
F. Riente , Electronics and Telecommunication Department, Politecnico di Torino, Corso Duca degli Abruzzi 24, Italy
M. Graziano , Electronics and Telecommunication Department, Politecnico di Torino, Corso Duca degli Abruzzi 24, Italy
M. Ruo Roch , Electronics and Telecommunication Department, Politecnico di Torino, Corso Duca degli Abruzzi 24, Italy
M. Zamboni , Electronics and Telecommunication Department, Politecnico di Torino, Corso Duca degli Abruzzi 24, Italy
pp. 1-6

Detection, diagnosis, and repair of faults in memristor-based memories (Abstract)

Sachhidh Kannan , Department of Electrical and Computer Engineering NYU Polytechnic School of Engineering Brooklyn, United States of America
Naghmeh Karimi , Department of Electrical and Computer Engineering NYU Polytechnic School of Engineering Brooklyn, United States of America
Ramesh Karri , Department of Electrical and Computer Engineering NYU Polytechnic School of Engineering Brooklyn, United States of America
Ozgur Sinanoglu , Department of Engineering New York University, Abu Dhabi Abu Dhabi, United Arab Emirates
pp. 1-6

Quality versus cost analysis for 3D Stacked ICs (Abstract)

Mottaqiallah Taouil , Delft University of Technology Faculty of EE, Mathematics and CS Mekelweg 4, 2628 CD Delft, The Netherlands
Said Hamdioui , Delft University of Technology Faculty of EE, Mathematics and CS Mekelweg 4, 2628 CD Delft, The Netherlands
Erik Jan Marinissen , IMEC vzw 3D Integration Program Kapeldreef 75, 3001 Leuven, Belgium
pp. 1-6

Test planning and test access mechanism design for stacked chips using ILP (Abstract)

Breeta SenGupta , Lund University Lund, Sweden
Erik Larsson , Lund University Lund, Sweden
pp. 1-6

SMV methodology enhancements for high speed I/O links of SoCs (Abstract)

Andres Viveros-Wacher , Intel Corporation, Intel Guadalajara Design Center, Anillo Periferico Sur 7980, Tlaquepaque, 45600, Mexico
Ricardo Alejos , Intel Corporation, Intel Guadalajara Design Center, Anillo Periferico Sur 7980, Tlaquepaque, 45600, Mexico
Liliana Alvarez , Intel Corporation, Intel Guadalajara Design Center, Anillo Periferico Sur 7980, Tlaquepaque, 45600, Mexico
Israel Diaz-Castro , Intel Corporation, Intel Guadalajara Design Center, Anillo Periferico Sur 7980, Tlaquepaque, 45600, Mexico
Brenda Marcial , Intel Corporation, Intel Guadalajara Design Center, Anillo Periferico Sur 7980, Tlaquepaque, 45600, Mexico
Gaston Motola-Acuna , Intel Corporation, Intel Guadalajara Design Center, Anillo Periferico Sur 7980, Tlaquepaque, 45600, Mexico
pp. 1-5

Extraction of threshold voltage degradation modeling due to Negative Bias Temperature Instability in circuits with I/O measurements (Abstract)

Soonyoung Cha , Georgia Tech, 30332, Atlanta, GA USA
Chang-Chih Chen , Georgia Tech, 30332, Atlanta, GA USA
Taizhi Liu , Georgia Tech, 30332, Atlanta, GA USA
Linda S. Milor , Georgia Tech, 30332, Atlanta, GA USA
pp. 1-6

At-speed interconnect testing and test-path optimization for 2.5D ICs (Abstract)

Ran Wang , ECE Dept., Duke University, Durham, NC, USA
Krishnendu Chakrabarty , ECE Dept., Duke University, Durham, NC, USA
Sudipta Bhawmik , Qualcomm Inc. Bridgewater, NJ, USA
pp. 1-6

Built-in self-test for manufacturing TSV defects before bonding (Abstract)

Giorgio Di Natale , LIRMM - Université Montpellier II/CNRS 161 rue Ada, Montpellier, France
Marie-lise Flottes , LIRMM - Université Montpellier II/CNRS 161 rue Ada, Montpellier, France
Bruno Rouzeyre , LIRMM - Université Montpellier II/CNRS 161 rue Ada, Montpellier, France
Hakim Zimouche , LIRMM - Université Montpellier II/CNRS 161 rue Ada, Montpellier, France
pp. 1-6

TSV aware timing analysis and diagnosis in paths with multiple TSVs (Abstract)

C. Metzler , LIRMM - University of Montpellier II / CNRS 161 rue Ada, 34095 Montpellier, France
A. Todri-Sanial , LIRMM - University of Montpellier II / CNRS 161 rue Ada, 34095 Montpellier, France
A. Bosio , LIRMM - University of Montpellier II / CNRS 161 rue Ada, 34095 Montpellier, France
L. Dilillo , LIRMM - University of Montpellier II / CNRS 161 rue Ada, 34095 Montpellier, France
P. Girard , LIRMM - University of Montpellier II / CNRS 161 rue Ada, 34095 Montpellier, France
A. Virazel , LIRMM - University of Montpellier II / CNRS 161 rue Ada, 34095 Montpellier, France
pp. 1-6

Reliability enhancement using in-field monitoring and recovery for RF circuits (Abstract)

Doohwang Chang , School of Electrical, Computer, and Energy Engineering Arizona State University
Sule Ozev , School of Electrical, Computer, and Energy Engineering Arizona State University
Bertan Bakkaloglu , School of Electrical, Computer, and Energy Engineering Arizona State University
Sayfe Kiaei , School of Electrical, Computer, and Energy Engineering Arizona State University
Engin Afacan , Department of Electrical and Electronics Engineering Bogazici University
Gunhan Dundar , Department of Electrical and Electronics Engineering Bogazici University
pp. 1-6

Continuous wave radar circuitry testing using OFDM technique (Abstract)

Mohamed Metwally , School of Engineering, University of Vermont
Nicholai L'Esperance , School of Engineering, University of Vermont
Tian Xia , School of Engineering, University of Vermont
Mustapha Slamani , RF/Mixed Signal Test Development, IBM Corporation
pp. 1-6

A built-in gain calibration technique for RF low-noise amplifiers (Abstract)

Ya-Ru Wu , Graduate Institute of Electronics Engineering National Taiwan University Taipei, Taiwan 106-17, R.O.C.
Yi-Keng Hsieh , Graduate Institute of Electronics Engineering National Taiwan University Taipei, Taiwan 106-17, R.O.C.
Po-Chih Ku , Graduate Institute of Electronics Engineering National Taiwan University Taipei, Taiwan 106-17, R.O.C.
Liang-Hung Lu , Graduate Institute of Electronics Engineering National Taiwan University Taipei, Taiwan 106-17, R.O.C.
pp. 1-6

Innovative practices session 7C: Reduced pin-count testing — How low can we go? (Abstract)

Stephen Sunter , Mentor Graphics
Steve Comen , Texas Instruments
Paul Berndt , Cypress Semiconductor
Ram Rajamani , Intel
pp. 1

Special session 8B — Panel: In-field testing of SoC devices: Which solutions by which players? (Abstract)

Jacob A. Abraham , University of Texas at Austin
Xinli Gu , Huawei Technologies
Janusz Rajski , Mentor Graphics
Paul G. Ryan , Intel
Dimitris Gizopoulos , University of Athens
Matteo Sonza Reorda , Politecnico di Torino
pp. 1-2

Special session 8C: Hot topic: Designers' and test researchers' roles in analog design-for-test (Abstract)

Masahiro Ishida , ADVANTEST Corporation
Takahiro J. Yamaguchi , ADVANTEST Laboratories, Ltd.
Mani Soma , Washington University
Terri Fiez , Oregon State University
Mike Peng Li , Altera Corporation
pp. 1

Identification of testable representative paths for low-cost verification of circuit performance during manufacturing and in-field tests (Abstract)

Jifeng Chen , ECE Department, University of Connecticut
LeRoy Winemberg , Freescale Semiconductor, Inc.
Mohammad Tehranipoor , ECE Department, University of Connecticut
pp. 1-6

Power/ground supply voltage variation-aware delay test pattern generation (Abstract)

Lu Wang , The University of Texas at San Antonio One UTSA Circle, San Antonio, TX, 78249
Xutao Wang , The University of Texas at San Antonio One UTSA Circle, San Antonio, TX, 78249
Milad Maleki , The University of Texas at San Antonio One UTSA Circle, San Antonio, TX, 78249
Bao Liu , The University of Texas at San Antonio One UTSA Circle, San Antonio, TX, 78249
pp. 1-6

Improved power supply noise control for pseudo functional test (Abstract)

Tengteng Zhang , Dept. of Computer Science and Engineering Texas A&M University College Station, Texas, US 77843
Duncan M. Hank Walker , Dept. of Computer Science and Engineering Texas A&M University College Station, Texas, US 77843
pp. 1-6

Phase-locked loop design with SPO detection and charge pump trimming for reference spur suppression (Abstract)

Sen-Wen Hsiao , School of Electrical and Computer Engineering, Georgia Institute of Technology, Atlanta, GA 30308 USA
Chung-Chun Chen , Silicon Creations, Suwanee, GA 30024
Randy Caplan , Silicon Creations, Suwanee, GA 30024
Jeff Galloway , Silicon Creations, Suwanee, GA 30024
Blake Gray , Silicon Creations, Suwanee, GA 30024
Abhijit Chatterjee , School of Electrical and Computer Engineering, Georgia Institute of Technology, Atlanta, GA 30308 USA
pp. 1-6

Development and empirical verification of an accuracy model for the power down leakage tests (Abstract)

Jae Woong Jeong , Arizona State University Electrical Engineering Tempe, AZ, USA
Sule Ozev , Arizona State University Electrical Engineering Tempe, AZ, USA
Friedrich Taenzler , Texas Instruments Dallas, Texas, USA
Hui-Chuan Chao , Texas Instruments Dallas, Texas, USA
pp. 1-6

A 4-GHz universal high-frequency on-chip testing platform for IP validation (Abstract)

Ping-Lin Yang , Taiwan Semiconductor Manufacturing Company (TSMC) Hsinchu, Taiwan, R.O.C.
Cheng-Chung Lin , Taiwan Semiconductor Manufacturing Company (TSMC) Hsinchu, Taiwan, R.O.C.
Ming-Zhang Kuo , Taiwan Semiconductor Manufacturing Company (TSMC) Hsinchu, Taiwan, R.O.C.
Sang-Hoo Dhong , Taiwan Semiconductor Manufacturing Company (TSMC) Hsinchu, Taiwan, R.O.C.
Chien-Min Lin , Taiwan Semiconductor Manufacturing Company (TSMC) Hsinchu, Taiwan, R.O.C.
Kevin Huang , Taiwan Semiconductor Manufacturing Company (TSMC) Hsinchu, Taiwan, R.O.C.
Ching-Nen Peng , Taiwan Semiconductor Manufacturing Company (TSMC) Hsinchu, Taiwan, R.O.C.
Min-Jer Wang , Taiwan Semiconductor Manufacturing Company (TSMC) Hsinchu, Taiwan, R.O.C.
pp. 1-6

A shared memory based parallel diagnosis system (Abstract)

X. Cai , Synopsys, Inc. Mountain View, CA, USA
E. Gizdarski , Synopsys, Inc. Mountain View, CA, USA
D. Landau , Synopsys, Inc. Mountain View, CA, USA
pp. 1-6

An efficient diagnosis method to deal with multiple fault-pairs simultaneously using a single circuit model (Abstract)

Cheng-Hung Wu , Department of Electrical Engineering, National Cheng Kung University, Tainan, Taiwan
Kuen-Jong Lee , Department of Electrical Engineering, National Cheng Kung University, Tainan, Taiwan
Wei-Cheng Lien , Department of Electrical Engineering, National Cheng Kung University, Tainan, Taiwan
pp. 1-6

Atomic model learning: A machine learning paradigm for post silicon debug of RF/analog circuits (Abstract)

Sabyasachi Deyati , Electrical & Computer Engineering, Georgia Institute of Technology, Atlanta GA 30332, USA
Barry J. Muldrey , Electrical & Computer Engineering, Georgia Institute of Technology, Atlanta GA 30332, USA
Aritra Banerjee , Electrical & Computer Engineering, Georgia Institute of Technology, Atlanta GA 30332, USA
Abhijit Chatterjee , Electrical & Computer Engineering, Georgia Institute of Technology, Atlanta GA 30332, USA
pp. 1-6

Functional block extraction for hardware security detection using time-integrated and time-resolved emission measurements (Abstract)

Franco Stellari , IBM T.J. Watson Research Center - 1101 Kitchawan Road, Yorktown Height, NY, 10598, USA
Peilin Song , IBM T.J. Watson Research Center - 1101 Kitchawan Road, Yorktown Height, NY, 10598, USA
Herschel A. Ainspan , IBM T.J. Watson Research Center - 1101 Kitchawan Road, Yorktown Height, NY, 10598, USA
pp. 1-6

Active defense against counterfeiting attacks through robust antifuse-based on-chip locks (Abstract)

Abhishek Basak , Department of EECS, Case Western Reserve University, Cleveland, OH 44106
Yu Zheng , Department of EECS, Case Western Reserve University, Cleveland, OH 44106
Swarup Bhunia , Department of EECS, Case Western Reserve University, Cleveland, OH 44106
pp. 1-6

Auto-identification of positive feedback loops in multi-state vulnerable circuits (Abstract)

Zhiqiang Liu , Dept. of Electrical and Computer Engineering Iowa State University Ames, IA 50010
You Li , Dept. of Electrical and Computer Engineering Iowa State University Ames, IA 50010
Randall L. Geiger , Dept. of Electrical and Computer Engineering Iowa State University Ames, IA 50010
Degang Chen , Dept. of Electrical and Computer Engineering Iowa State University Ames, IA 50010
pp. 1-5

On the use of multi-cycle tests for storage of two-cycle broadside tests (Abstract)

Irith Pomeranz , School of Electrical & Computer Eng. Purdue University West Lafayette, IN 47907, U.S.A.
pp. 1-6

Test-time optimization in NOC-based manycore SOCs using multicast routing (Abstract)

Mukesh Agrawal , Department of Electrical & Computer Engineering Duke University, Durham, NC 27708
Krishnendu Chakrabarty , Department of Electrical & Computer Engineering Duke University, Durham, NC 27708
pp. 1-6

On-chip voltage-droop prediction using support-vector machines (Abstract)

Fangming Ye , ECE Dept., Duke University, Durham, NC, USA
Farshad Firouzi , Karlsruhe Institute of Technology, Germany
Yang Yang , ECE Dept., Duke University, Durham, NC, USA
Krishnendu Chakrabarty , ECE Dept., Duke University, Durham, NC, USA
Mehdi B. Tahoori , Karlsruhe Institute of Technology, Germany
pp. 1-6
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