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2013 IEEE 31st VLSI Test Symposium (VTS) (2013)
Berkeley, CA, USA USA
Apr. 29, 2013 to May 2, 2013
ISSN: 1093-0167
ISBN: 978-1-4673-5542-1
TABLE OF CONTENTS

Experiments and analysis to characterize logic state retention limitations in 28nm process node (Abstract)

S. Dasnurkar , Qualcomm Inc., San Diego, CA, USA
A. Datta , Qualcomm Inc., San Diego, CA, USA
M. Abu-Rahma , Qualcomm Inc., San Diego, CA, USA
H. Nguyen , Qualcomm Inc., San Diego, CA, USA
M. Villafana , Qualcomm Inc., San Diego, CA, USA
H. Rasouli , Qualcomm Inc., San Diego, CA, USA
S. Tamjidi , Qualcomm Inc., San Diego, CA, USA
Ming Cai , Qualcomm Inc., San Diego, CA, USA
S. Sengupta , Qualcomm Inc., San Diego, CA, USA
P. R. Chidambaram , Qualcomm Inc., San Diego, CA, USA
R. Thirumala , Qualcomm Inc., San Diego, CA, USA
N. Kulkarni , Qualcomm Inc., San Diego, CA, USA
P. Seeram , Qualcomm Inc., San Diego, CA, USA
P. Bhadri , Qualcomm Inc., San Diego, CA, USA
P. Patel , Qualcomm Inc., San Diego, CA, USA
Sei Seung Yoon , Qualcomm Inc., San Diego, CA, USA
E. Terzioglu , Qualcomm Inc., San Diego, CA, USA
pp. 1-6

Testing retention flip-flops in power-gated designs (Abstract)

Hao-Wen Hsu , Dept. of Electron. Eng., Nat. Chiao Tung Univ., Hsinchu, Taiwan
Shih-Hua Kuo , Dept. of Electron. Eng., Nat. Chiao Tung Univ., Hsinchu, Taiwan
Wen-Hsiang Chang , Dept. of Electron. Eng., Nat. Chiao Tung Univ., Hsinchu, Taiwan
Shi-Hao Chen , Global Unichip Corp, Hsinchu, Taiwan
Ming-Tung Chang , Global Unichip Corp, Hsinchu, Taiwan
Mango C.-T Chao , Dept. of Electron. Eng., Nat. Chiao Tung Univ., Hsinchu, Taiwan
pp. 1-6

Power supply noise control in pseudo functional test (Abstract)

Tengteng Zhang , Dept. of Comput. Sci. & Eng., Texas A&M Univ., College Station, TX, USA
Duncan M. Hank Walker , Dept. of Comput. Sci. & Eng., Texas A&M Univ., College Station, TX, USA
pp. 1-6

Finding best voltage and frequency to shorten power-constrained test time (Abstract)

P. Venkataramani , Dept. of Electr. & Comput. Eng., Auburn Univ., Auburn, AL, USA
S. Sindia , Dept. of Electr. & Comput. Eng., Auburn Univ., Auburn, AL, USA
V. D. Agrawal , Dept. of Electr. & Comput. Eng., Auburn Univ., Auburn, AL, USA
pp. 1-6

SOC test compression scheme using sequential linear decompressors with retained free variables (Abstract)

S. S. Muthyala , Comput. Eng. Res. Center, Univ. of Texas, Austin, TX, USA
N. A. Touba , Comput. Eng. Res. Center, Univ. of Texas, Austin, TX, USA
pp. 1-6

Selection of tests for outlier detection (Abstract)

H. C. M. Bossers , Dept. of Electr. Eng., Math. & Comput. Sci., Univ. of Twente, Enschede, Netherlands
J. L. Hurink , Dept. of Electr. Eng., Math. & Comput. Sci., Univ. of Twente, Enschede, Netherlands
G. J. M. Smit , Dept. of Electr. Eng., Math. & Comput. Sci., Univ. of Twente, Enschede, Netherlands
pp. 1-6

Tracing the best test mix through multi-variate quality tracking (Abstract)

B. Arslan , Comput. Sci. & Eng., Univ. of California, San Diego, La Jolla, CA, USA
A. Orailoglu , Comput. Sci. & Eng., Univ. of California, San Diego, La Jolla, CA, USA
pp. 1-6

Measurement of envelope/phase path delay skew and envelope path bandwidth in polar transmitters (Abstract)

Jae Woong Jeong , Electr. Eng., Arizona State Univ., Tempe, AZ, USA
S. Ozev , Electr. Eng., Arizona State Univ., Tempe, AZ, USA
S. Sen , Intel Corp., Hillsboro, OR, USA
T. M. Mak , Intel Corp., Hillsboro, OR, USA
pp. 1-6

Defect-oriented non-intrusive RF test using on-chip temperature sensors (Abstract)

L. Abdallah , TIMA Lab., Grenoble INP-UJF, Grenoble, France
H. Stratigopoulos , TIMA Lab., Grenoble INP-UJF, Grenoble, France
S. Mir , TIMA Lab., Grenoble INP-UJF, Grenoble, France
J. Altet , Dept. of Electron. Eng., Univ. Politec. de Catalunya, Barcelona, Spain
pp. 1-6

Novel estimation method of EVM with channel correction for linear impairments in multi-standard RF transceivers (Abstract)

K. Asami , Advantest Corp., Gunma, Japan
T. Shimura , Advantest Corp., Gunma, Japan
T. Kurihara , Advantest Corp., Gunma, Japan
pp. 1-6

A built-in scheme for testing and repairing voltage regulators of low-power srams (Abstract)

L. B. Zordan , LIRMM, Univ. Montpellier II, Montpellier, France
A. Bosio , LIRMM, Univ. Montpellier II, Montpellier, France
L. Dilillo , LIRMM, Univ. Montpellier II, Montpellier, France
P. Girard , LIRMM, Univ. Montpellier II, Montpellier, France
A. Todri , LIRMM, Univ. Montpellier II, Montpellier, France
A. Virazel , LIRMM, Univ. Montpellier II, Montpellier, France
N. Badereddine , Intel Mobile Commun., Sophia-Antipolis, France
pp. 1-6

Testing of a low-VMIN data-aware dynamic-supply 8T SRAM (Abstract)

Chen-Wei Lin , Dept. of Electron. Eng., Nat. Chiao Tung Univ., Hsinchu, Taiwan
Chin-Yuan Huang , Dept. of Electron. Eng., Nat. Chiao Tung Univ., Hsinchu, Taiwan
Mango C.-T Chao , Dept. of Electron. Eng., Nat. Chiao Tung Univ., Hsinchu, Taiwan
pp. 1-6

Special session 4C: Hot topic 3D-IC design and test (Abstract)

Jin-Fu Li , National Central University
Cheng-Wen Wu , ITRI/NTHU
Cheng-Wen Wu , ITRI/NTHU
Masahiro Aoyagi , AIST, Japan
Meng-Fan Marvin Chang , NTHU, Taiwan
Ding-Ming Kwai , ITRI, Taiwan
pp. 1

Extending pre-silicon delay models for post-silicon tasks: Validation, diagnosis, delay testing, and speed binning (Abstract)

P. Das , Dept. of Electr. Eng.-Syst., Univ. of Southern California, Los Angeles, CA, USA
S. K. Gupta , Dept. of Electr. Eng.-Syst., Univ. of Southern California, Los Angeles, CA, USA
pp. 1-6

Path selection based on static timing analysis considering input necessary assignments (Abstract)

Bo Yao , Sch. of Electr. & Comput. Eng., Purdue Univ., West Lafayette, IN, USA
A. Sinha , Intel Corp., Hillsboro, OR, USA
I. Pomeranz , Sch. of Electr. & Comput. Eng., Purdue Univ., West Lafayette, IN, USA
pp. 1-6

Scalable dynamic technique for accurately predicting power-supply noise and path delay (Abstract)

S. K. Rao , CSEE Dept., Univ. of Maryland, Baltimore, MD, USA
R. Robucci , CSEE Dept., Univ. of Maryland, Baltimore, MD, USA
C. Patel , CSEE Dept., Univ. of Maryland, Baltimore, MD, USA
pp. 1-6

Contactless test access mechanism for TSV based 3D ICs (Abstract)

R. Rashidzadeh , Dept. of Electr. & Comput. Eng., Univ. of Windsor, Windsor, ON, Canada
pp. 1-6

3D-IC interconnect test, diagnosis, and repair (Abstract)

Chun-Chuan Chi , Dept. of Electr. Eng., Nat. Tsing Hua Univ., Hsinchu, Taiwan
Cheng-Wen Wu , Dept. of Electr. Eng., Nat. Tsing Hua Univ., Hsinchu, Taiwan
Min-Jer Wang , Taiwan Semicond. Manuf. Co. (TSMC), Hsinchu, Taiwan
Hung-Chih Lin , Taiwan Semicond. Manuf. Co. (TSMC), Hsinchu, Taiwan
pp. 1-6

Testing of flow-based microfluidic biochips (Abstract)

Kai Hu , ECE Dept., Duke Univ., Durham, NC, USA
Tsung-Yi Ho , Nat. Cheng Kung Univ., Tainan, Taiwan
K. Chakrabarty , ECE Dept., Duke Univ., Durham, NC, USA
pp. 1-6

Innovative practices session 5C: Cloud atlas — Unreliability through massive connectivity (Abstract)

Helia Naeimi , Intel Corporation
Suriya Natarajan , Intel Corporation
Kushagra Vaid , Microsoft Corporation
Prabhakar Kudva , IBM Corporation
Mahesh Natu , Intel Corporation
pp. 1

A framework for low overhead hardware based runtime control flow error detection and recovery (Abstract)

A. Chaudhari , Comput. Eng. Res. Center, Univ. of Texas at Austin, Austin, TX, USA
Junyoung Park , Comput. Eng. Res. Center, Univ. of Texas at Austin, Austin, TX, USA
J. Abraham , Comput. Eng. Res. Center, Univ. of Texas at Austin, Austin, TX, USA
pp. 1-6

Trading off area, yield and performance via hybrid redundancy in multi-core architectures (Abstract)

Yue Gao , Ming Hsieh Dept. of Electr. Eng., Univ. of Southern California, Los Angeles, CA, USA
Yang Zhang , Ming Hsieh Dept. of Electr. Eng., Univ. of Southern California, Los Angeles, CA, USA
Da Cheng , Ming Hsieh Dept. of Electr. Eng., Univ. of Southern California, Los Angeles, CA, USA
M. A. Breuer , Ming Hsieh Dept. of Electr. Eng., Univ. of Southern California, Los Angeles, CA, USA
pp. 1-6

Combining checkpointing and scrubbing in FPGA-based real-time systems (Abstract)

Aitzan Sari , Dept. of Inf., Univ. of Piraeus, Piraeus, Greece
M. Psarakis , Dept. of Inf., Univ. of Piraeus, Piraeus, Greece
D. Gizopoulos , Dept. of Inf. & Telecommun., Univ. of Athens, Athens, Greece
pp. 1-6

An IDDQ BIST approach to characterize phase-locked loop parameters (Abstract)

S. Maltabas , Univ. of Massachusetts Lowell, Lowell, MA, USA
O. K. Ekekon , Intel Corp., Hillsboro, OR, USA
K. Kulovic , Maxim Integrated, Chelmsford, MA, USA
A. Meixner , Intel Corp., Hillsboro, OR, USA
M. Margala , Univ. of Massachusetts Lowell, Lowell, MA, USA
pp. 1-6

A programmable BIST design for PLL static phase offset estimation and clock duty cycle detection (Abstract)

Sen-Wen Hsiao , Sch. of Electr. & Comput. Eng., Georgia Inst. of Technol. Atlanta, Atlanta, GA, USA
Nicholas Tzou , Sch. of Electr. & Comput. Eng., Georgia Inst. of Technol. Atlanta, Atlanta, GA, USA
A. Chatterjee , Sch. of Electr. & Comput. Eng., Georgia Inst. of Technol. Atlanta, Atlanta, GA, USA
pp. 1-6

Reduced code linearity testing of pipeline adcs in the presence of noise (Abstract)

A. Laraba , TIMA Lab., Grenoble INP-UJF, Grenoble, France
H. Stratigopoulos , TIMA Lab., Grenoble INP-UJF, Grenoble, France
S. Mir , TIMA Lab., Grenoble INP-UJF, Grenoble, France
H. Naudet , STMicroelectron., Grenoble, France
G. Bret , STMicroelectron., Grenoble, France
pp. 1-6

Innovative practices session 6C: Latest practices in test compression (Abstract)

J. Colburn , NVIDIA Corporation
K.-Y. Chung , Samsung Electronics Co.
H. Konuk , Broadcom Corporation
Y. Dong , Advanced Micro Devices, Inc.
pp. 1

Enhanced algorithm of combining trace and scan signals in post-silicon validation (Abstract)

Kihyuk Han , GPU Design Dept., Samsung Austin R&D Center (SARC), Austin, TX, USA
Joon-Sung Yang , Sungkyunkwan Univ., Suwon, South Korea
J. A. Abraham , Comput. Eng. Res. Center, Univ. of Texas at Austin, Austin, TX, USA
pp. 1-6

Distributed dynamic partitioning based diagnosis of scan chain (Abstract)

Yu Huang , Mentor Graphics, Wilsonville, OR, USA
Xiaoxin Fan , Dept. of ECE, Univ. of Iowa, Iowa City, IA, USA
Huaxing Tang , Mentor Graphics, Wilsonville, OR, USA
M. Sharma , Mentor Graphics, Wilsonville, OR, USA
Wu-Tung Cheng , Mentor Graphics, Wilsonville, OR, USA
B. Benware , Mentor Graphics, Wilsonville, OR, USA
S. M. Reddy , Dept. of ECE, Univ. of Iowa, Iowa City, IA, USA
pp. 1-6

RAVAGE: Post-silicon validation of mixed signal systems using genetic stimulus evolution and model tuning (Abstract)

B. Muldrey , Sch. of Electr. & Comput. Eng., Georgia Inst. of Technol., Atlanta, GA, USA
S. Deyati , Sch. of Electr. & Comput. Eng., Georgia Inst. of Technol., Atlanta, GA, USA
M. Giardino , Sch. of Electr. & Comput. Eng., Georgia Inst. of Technol., Atlanta, GA, USA
A. Chatterjee , Sch. of Electr. & Comput. Eng., Georgia Inst. of Technol., Atlanta, GA, USA
pp. 1-6

Innovative practices session 7C: Self-calibration & trimming (Abstract)

Yiorgos Makris , The University of Texas at Dallas
C. Thibeault , E. Sup. Tech. Montreal
pp. 1

Special session 8B: Embedded tutorial challenges in SSD (Abstract)

Manuel d'Abreu , NAND Flash Memory: the Driving Technology in Digital Storage Manuel d'Abreu, SanDisk
Amitava Mazumdar , NAND-Based Storage: Challenges and System Solutions Xinde Hu, SanDisk
pp. 1

A study on the effectiveness of Trojan detection techniques using a red team blue team approach (Abstract)

X. Zhang , Dept. of Electr. & Comput. Eng., Univ. of Connecticut, Storrs, CT, USA
K. Xiao , Dept. of Electr. & Comput. Eng., Univ. of Connecticut, Storrs, CT, USA
M. Tehranipoor , Dept. of Electr. & Comput. Eng., Univ. of Connecticut, Storrs, CT, USA
J. Rajendran , Dept. of Electr. & Comput. Eng., Polytech. Inst. of New York Univ., New York, NY, USA
R. Karri , Dept. of Electr. & Comput. Eng., Polytech. Inst. of New York Univ., New York, NY, USA
pp. 1-3

A multi-parameter functional side-channel analysis method for hardware trust verification (Abstract)

C. Bell , Dept. of Comput. Sci. & Eng., Univ. of South Florida, Tampa, FL, USA
M. Lewandowski , Dept. of Comput. Sci. & Eng., Univ. of South Florida, Tampa, FL, USA
S. Katkoori , Dept. of Comput. Sci. & Eng., Univ. of South Florida, Tampa, FL, USA
pp. 1-4

Experiences in side channel and testing based Hardware Trojan detection (Abstract)

D. Hely , Esisar-LCIS, Grenoble Inst. of Technol., Valence, France
J. Martin , Esisar-LCIS, Grenoble Inst. of Technol., Valence, France
G. D. P. Triana , Esisar-LCIS, Grenoble Inst. of Technol., Valence, France
S. P. Mounier , Esisar-LCIS, Grenoble Inst. of Technol., Valence, France
E. Riviere , Esisar-LCIS, Grenoble Inst. of Technol., Valence, France
T. Sahuc , Esisar-LCIS, Grenoble Inst. of Technol., Valence, France
J. Savonet , Esisar-LCIS, Grenoble Inst. of Technol., Valence, France
L. Soundararadjou , Esisar-LCIS, Grenoble Inst. of Technol., Valence, France
pp. 1-4

A multi-faceted approach to FPGA-based Trojan circuit detection (Abstract)

M. Patterson , Electr. & Comput. Eng., Iowa State Univ., Ames, IA, USA
A. Mills , Electr. & Comput. Eng., Iowa State Univ., Ames, IA, USA
R. Scheel , Electr. & Comput. Eng., Iowa State Univ., Ames, IA, USA
J. Tillman , Electr. & Comput. Eng., Iowa State Univ., Ames, IA, USA
E. Dye , Electr. & Comput. Eng., Iowa State Univ., Ames, IA, USA
J. Zambreno , Electr. & Comput. Eng., Iowa State Univ., Ames, IA, USA
pp. 1-4

Towards a cost-effective hardware trojan detection methodology (Abstract)

R. Paseman , Comput. Sci. & Eng., Univ. of California at San Diego, La Jolla, CA, USA
A. Orailoglu , Comput. Sci. & Eng., Univ. of California at San Diego, La Jolla, CA, USA
pp. 1-3

A hybrid ECC and redundancy technique for reducing refresh power of DRAMs (Abstract)

Yun-Chao Yu , Dept. of Electr. Eng., Nat. Central Univ., Jhongli, Taiwan
Chih-Sheng Hou , Dept. of Electr. Eng., Nat. Central Univ., Jhongli, Taiwan
Li-Jung Chang , Dept. of Electr. Eng., Nat. Central Univ., Jhongli, Taiwan
Jin-Fu Li , Dept. of Electr. Eng., Nat. Central Univ., Jhongli, Taiwan
Chih-Yen Lo , Inf. & Commun. Res. Labs., Ind. Technol. Res. Inst., Hsinchu, Taiwan
Ding-Ming Kwai , Inf. & Commun. Res. Labs., Ind. Technol. Res. Inst., Hsinchu, Taiwan
Yung-Fa Chou , Inf. & Commun. Res. Labs., Ind. Technol. Res. Inst., Hsinchu, Taiwan
Cheng-Wen Wu , Inf. & Commun. Res. Labs., Ind. Technol. Res. Inst., Hsinchu, Taiwan
pp. 1-6

Investigation of gate oxide short in FinFETs and the test methods for FinFET SRAMs (Abstract)

Chen-Wei Lin , Dept. of Electron. Eng., Nat. Chiao Tung Univ., Hsinchu, Taiwan
M. C.-T Chao , Dept. of Electron. Eng., Nat. Chiao Tung Univ., Hsinchu, Taiwan
Chih-Chieh Hsu , Ind. Technol. Res. Inst., Hsinchu, Taiwan
pp. 1-6

On the investigation of built-in tuning of RF receivers using on-chip polyphase filters (Abstract)

F. Haddad , IM2NP, IMT, Aix-Marseille Univ., Marseille, France
W. Rahajandraibe , IM2NP, IMT, Aix-Marseille Univ., Marseille, France
H. Aziza , IM2NP, IMT, Aix-Marseille Univ., Marseille, France
K. Castellani-Coulie , IM2NP, IMT, Aix-Marseille Univ., Marseille, France
J.-M Portal , IM2NP, IMT, Aix-Marseille Univ., Marseille, France
pp. 1-6

On-chip circuit for measuring multi-GHz clock signal waveforms (Abstract)

K. A. Jenkins , IBM T. J. Watson Res. Center, Yorktown Heights, NY, USA
P. Restle , IBM T. J. Watson Res. Center, Yorktown Heights, NY, USA
P. Z. Wang , IBM Syst. &Technol. Group, Austin, TX, USA
D. Hogenmiller , IBM Syst. &Technol. Group, Austin, TX, USA
D. Boerstler , IBM Syst. &Technol. Group, Austin, TX, USA
T. Bucelot , IBM T. J. Watson Res. Center, Yorktown Heights, NY, USA
pp. 1-4

Low-cost multi-channel testing of periodic signals using monobit receivers and incoherent subsampling (Abstract)

Thomas Moon , Sch. of ECE, Georgia Tech, Atlanta, GA, USA
Hyun Woo Choi , Samsung Electron., San Jose, CA, USA
A. Chatterjee , Sch. of ECE, Georgia Tech, Atlanta, GA, USA
pp. 1-6

Chip-level modeling and analysis of electrical masking of soft errors (Abstract)

S. Kiamehr , Dept. of Comput. Sci., Karlsruhe Inst. of Technol., Karlsruhe, Germany
M. Ebrahimi , Dept. of Comput. Sci., Karlsruhe Inst. of Technol., Karlsruhe, Germany
F. Firouzi , Dept. of Comput. Sci., Karlsruhe Inst. of Technol., Karlsruhe, Germany
M. B. Tahoori , Dept. of Comput. Sci., Karlsruhe Inst. of Technol., Karlsruhe, Germany
pp. 1-6

Identification of critical variables using an FPGA-based fault injection framework (Abstract)

A. Riefert , Albert-Ludwigs-Univ. Freiburg, Freiburg, Germany
J. Muller , Albert-Ludwigs-Univ. Freiburg, Freiburg, Germany
M. Sauer , Albert-Ludwigs-Univ. Freiburg, Freiburg, Germany
W. Burgard , Albert-Ludwigs-Univ. Freiburg, Freiburg, Germany
B. Becker , Albert-Ludwigs-Univ. Freiburg, Freiburg, Germany
pp. 1-6

RSAK: Random stream attack for phase change memory in video applications (Abstract)

Yuntan Fang , State Key Lab. of Comput. Archit. Inst. of Comput. Technol., Beijing, China
Huawei Li , State Key Lab. of Comput. Archit. Inst. of Comput. Technol., Beijing, China
Xiaowei Li , State Key Lab. of Comput. Archit. Inst. of Comput. Technol., Beijing, China
pp. 1-6

Innovative practices session 10C: Delay test (Abstract)

P. Pant , Intel Corporation (USA)
M. Amodeo , Cadence Design Systems (USA)
S. Vora , Intel Corporation (USA)
J. Colburn , NVIDIA Corporation (USA)
pp. 1

Post-DfT-insertion retiming for delay recovery on inter-die paths in 3D ICs (Abstract)

B. Noia , Dept. Electr. & Comput. Eng., Duke Univ., Durham, NC, USA
K. Chakrabarty , Dept. Electr. & Comput. Eng., Duke Univ., Durham, NC, USA
pp. 1-6

Allocation of RAM built-in self-repair circuits for SOC dies of 3D ICs (Abstract)

Chih-Sheng Hou , Dept. of Electr. Eng., Nat. Central Univ., Jhongli, Taiwan
Jin-Fu Li , Dept. of Electr. Eng., Nat. Central Univ., Jhongli, Taiwan
pp. 1-6

Test-cost optimization and test-flow selection for 3D-stacked ICs (Abstract)

M. Agrawal , Dept. of Electr. & Comput. Eng., Duke Univ., Durham, NC, USA
K. Chakrabarty , Dept. of Electr. & Comput. Eng., Duke Univ., Durham, NC, USA
pp. 1-6

Innovative practices session 11C: Resilience (Abstract)

Mohan J. Kumar , Lead SW and RAS Architect, Intel DCSG
pp. 1

Special session 12B: Panel post-silicon validation & test in huge variance era (Abstract)

Takahiro J. Yamaguchi , Advantest Laboratories Ltd./University of Tokyo
Jacob A. Abraham , Universityof Texas at Austin
Gordon W. Roberts , McGill University
Dennis Ciplickas , PDF Solutions
pp. 1
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