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2013 IEEE 31st VLSI Test Symposium (VTS) (2008)
Apr. 27, 2008 to May 1, 2008
ISSN: 1093-0167
ISBN: 0-7695-3123-7
pp: 139-146
ABSTRACT
Power consumption during scan-based test becomes a concern in nanometer technologies. Previous test power reduction techniques that insert additional logic in gate-level circuits may result in timing violations. In this paper, we show that the problem can be solved at the RTL instead so that the timing and area constraints will be handled automatically by synthesis tools. Using a signal probabilistic approach proposed previously, we identify power-sensitive scan cells at the prototyping gate level, and we map these cells to their corresponding signal / variable bits at the RT-Level. Additional RTL code is added to freeze these power sensitive bits in order to reduce scan shift power consumption. Experimental results on ITC99 benchmarks show that on average more than 22% power reduction can be achieved when we only freeze the top 1% of power-sensitive bits at RTL. The flow is more practical in terms of timing closure than doing the same at the gate-level.
INDEX TERMS
Scan Based Test, Test Power Reduction, Power-Sensitive Scan Cell, RTL DFT, Timing Closure
CITATION
Yu Huang, Wu-Tung Cheng, Jennifer Dworak, Elif Alpaslan, Xijiang Lin, "Reducing Scan Shift Power at RTL", 2013 IEEE 31st VLSI Test Symposium (VTS), vol. 00, no. , pp. 139-146, 2008, doi:10.1109/VTS.2008.36
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