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2013 IEEE 31st VLSI Test Symposium (VTS) (2007)
Berkeley, California
May 6, 2007 to May 10, 2007
ISSN: 1093-0167
ISBN: 0-7695-2812-0
TABLE OF CONTENTS
Introduction

Foreword (PDF)

pp. xiii

Organizing Committee (PDF)

pp. xiv-xv

Program Committee (PDF)

pp. xvii

Reviewers (PDF)

pp. xviii-xix

Awards (PDF)

pp. xxviii
Session 1A: RF Test I

A Low-Cost RF MIMO Test Method Using a Single Measurement Set-up (Abstract)

Erkan Acar , Duke University Durham, USA
Sule Ozev , Duke University Durham, USA
Kevin B. Redmond , Intel Corporation Hillsboro, USA
pp. 3-8

Non-RF to RF Test Correlation Using Learning Machines: A Case Study (Abstract)

Haralampos-G.D. Stratigopoulos , TIMA Laboratory, France
Petros Drineas , Rensselaer Polytechnic Institute, USA
Mustapha Slamani , IBM, USA
Yiorgos Makris , Yale University, USA
pp. 9-14

RF Digital Signal Generation Beyond Nyquist (Abstract)

Marcelo Negreiros , Universidade Federal do Rio Grande do Sul, Brazil
Ad? Souza Jr. , CEFET-RS, Brazil
Luigi Carro , Universidade Federal do Rio Grande do Sul, Brazil
Altamiro Amadeu Susin , Universidade Federal do Rio Grande do Sul, Brazil
pp. 15-22
Session 1B: Delay Test Quality

Delay Test Quality Evaluation Using Bounded Gate Delays (Abstract)

Soumitra Bose , Design Technology, Intel Corp., USA
Vishwani D. Agrawal , Auburn University, USA
pp. 23-28

On Performance Testing with Path Delay Patterns (Abstract)

Bram Kruseman , NXP Semiconductors, The Netherlands
Ananta Majhi , NXP Semiconductors, The Netherlands
Guido Gronthoud , NXP Semiconductors, The Netherlands
pp. 29-34

Power Virus Generation Using Behavioral Models of Circuits (Abstract)

K. Najeeb , Indian Institute of Technology, India
Vishnu Vardhan Reddy Konda , Indian Institute of Technology, India
Siva Kumar Sastry Hari , Indian Institute of Technology, India
V. Kamakoti , Indian Institute of Technology, India
Vivekananda M Vedula , Intel Corporation, USA
pp. 35-42
IP Session 1C: Design in the Presence of Variations: Characterization, Monitoring, and Response
Session 2A: Memory Test

Retention and Reliability Problems in Embedded Flash Memories: Analysis and Test of Defective 2T-FLOTOX Tunnel Window (Abstract)

O. Ginez , Universite de Montpellier II/CNRS, France; ATMEL Rousset, France
J.-M. Daga , ATMEL Rousset, France
P. Girard , Universite de Montpellier II/CNRS, France
C. Landrault , Universite de Montpellier II/CNRS, France
S. Pravossoudovitch , Universite de Montpellier II/CNRS, France
A. Virazel , Universite de Montpellier II/CNRS, France
pp. 47-52

SDRAM Delay Fault Modeling and Performance Testing (Abstract)

Yu-Tsao Hsing , National Tsing Hua University, Taiwan
Chun-Chieh Huang , National Tsing Hua University, Taiwan
Jen-Chieh Yeh , National Tsing Hua University, Taiwan
Cheng-Wen Wu , National Tsing Hua University, Taiwan
pp. 53-58

Optimizing Test Length for Soft Faults in DRAM Devices (Abstract)

Zaid Al-Ars , Delft University of Technology, The Netherlands
Said Hamdioui , Delft University of Technology, The Netherlands
Georgi Gaydadjiev , Delft University of Technology, The Netherlands
pp. 59-66
Session 2B: Test Compression

Minimizing the Impact of Scan Compression (Abstract)

P. Wohl , Synopsys, Inc.
J.A. Waicukauski , Synopsys, Inc.
R. Kapur , Synopsys, Inc.
S. Ramnath , Synopsys, Inc.
E. Gizdarski , Synopsys, Inc.
T.W. Williams , Synopsys, Inc.
P. Jaini , Synopsys, Inc.
pp. 67-74

Low Power Embedded Deterministic Test (Abstract)

Dariusz Czysz , Poznan University of Technology, Poland
Grzegorz Mrugalski , Mentor Graphics Corporation, USA
Janusz Rajski , Mentor Graphics Corporation, USA
Jerzy Tyszer , Poznan University of Technology, Poland
pp. 75-83

Multimode Illinois Scan Architecture for Test Application Time and Test Data Volume Reduction (Abstract)

Anshuman Chandra , Synopsys, Inc., USA
Haihua Yan , Synopsys, Inc., USA
Rohit Kapur , Synopsys, Inc., USA
pp. 84-92
IP Session 2C: Small Delay Test in Practice
Session 3A: Going after Defects

On a New Outlier Rejection Technique (Abstract)

C. Thibeault , Ecole de technologie superieure, Canada
pp. 97-103

Enhanced Resolution Jitter Testing Using Jitter Expansion (Abstract)

Hyun Choi , Georgia Institute of Technology, USA
Donghoon Han , Georgia Institute of Technology, USA
Abhijit Chatterjee , Georgia Institute of Technology, USA
pp. 104-109

Using Clock-Vdd to Test and Diagnose the Power-Switch in Power-Gating Circuit (Abstract)

Hsiang-Hui Huang , Feng-Chia University, Taiwan
Ching-Hwa Cheng , Feng-Chia University, Taiwan
pp. 110-118
Session 3B: Online Test

A Programmable Window Comparator for Analog Online Testing (Abstract)

Amit Laknaur , Southern Illinois University, USA
Rui Xiao , Southern Illinois University, USA
Haibo Wang , Southern Illinois University, USA
pp. 119-124

Probabilistic Compensation for Digital Filters Using Pervasive Noise-Induced Operator Errors (Abstract)

Maryam Ashouei , Georgia Institute of Technology, USA
Soumendu Bhattacharya , Georgia Institute of Technology, USA
Abhijit Chatterjee , Georgia Institute of Technology, USA
pp. 125-130

Error Tolerance in DNA Self-Assembly by (2k-1) x (2k-1) Snake Tile Sets (Abstract)

X. Ma , Northeastern University, USA
J. Huang , Northeastern University, USA
F. Lombardi , Northeastern University, USA
pp. 131-140
IP Session 3C: System Test and NTFs

Session Abstract (PDF)

pp. 141
Session 4A: Diagnosis I

Diagnosis of Bridging Defects Based on Current Signatures at Low Power Supply Voltages (Abstract)

D. Arumi , Universitat Politecnica de Catalunya, Spain
R. Rodriguez-Montanes , Universitat Politecnica de Catalunya, Spain
J. Figueras , Universitat Politecnica de Catalunya, Spain
S. Eichenberger , NXP Semiconductors, The Netherlands
C. Hora , NXP Semiconductors, The Netherlands
B. Kruseman , NXP Semiconductors, The Netherlands
M. Lousberg , NXP Semiconductors, The Netherlands
A.K. Majhi , NXP Semiconductors, The Netherlands
pp. 145-150

Handling Pattern-Dependent Delay Faults in Diagnosis (Abstract)

Jyun-Wei Chen , National Tsing Hua University, Taiwan
Ying-Yen Chen , National Tsing Hua University, Taiwan
Jing-Jia Liou , National Tsing Hua University, Taiwan
pp. 151-157

Diagnosis of Full Open Defects in Interconnecting Lines (Abstract)

R. Rodriguez-Montanes , Universitat Politecnica de Catalunya, Spain
D. Arumi , Universitat Politecnica de Catalunya, Spain
J. Figueras , Universitat Politecnica de Catalunya, Spain
S. Einchenberger , NXP Semiconductors, The Netherlands
C. Hora , NXP Semiconductors, The Netherlands
B. Kruseman , NXP Semiconductors, The Netherlands
M. Lousberg , NXP Semiconductors, The Netherlands
A.K. Majhi , NXP Semiconductors, The Netherlands
pp. 158-166
Session 4B: ATPG for Delay Faults

Glitch-Aware Pattern Generation and Optimization Framework for Power-Safe Scan Test (Abstract)

V.R. Devanathan , Texas Instruments India Pvt. Ltd., India
C.P. Ravikumar , Texas Instruments India Pvt. Ltd., India
V. Kamakoti , Indian Institute of Technology, India
pp. 167-172

An Integrated Framework for At-Speed and ATE-Driven Delay Test of Contract-Manufactured ASICs (Abstract)

Vikram Iyengar , IBM Microelectronics, USA
Kenneth Pichamuthu , IBM Global Engineering Solutions, India
Andy Ferko , IBM Microelectronics, USA
Frank Woytowich , IBM Microelectronics, USA
Dave Lackey , IBM Microelectronics, USA
Gary Grise , IBM Microelectronics, USA
Mark Taylor , IBM Microelectronics, USA
Mike Degregorio , IBM Microelectronics, USA
Steve Oakland , IBM Microelectronics, USA
pp. 173-178

Supply Voltage Noise Aware ATPG for Transition Delay Faults (Abstract)

Nisar Ahmed , University of Connecticut, USA
Mohammad Tehranipoor , University of Connecticut, USA
Vinay Jayaram , Texas Instruments, Inc., USA
pp. 179-186
IP Session 4C: High-Speed Test

Session Abstract (PDF)

pp. 187
Special Session 5A: Embedded Tutorial--Statistical and Data Mining Methods for Test-Based Yield Learning

Session Abstract (PDF)

pp. 191
Special Session 5B: Panel--Conversations with Test Experts

Session Abstract (PDF)

pp. 195
Session 6A: Advances in Test

Test Set Reordering Using the Gate Exhaustive Test Metric (Abstract)

Kyoung Youn Cho , Stanford University, USA
Edward J. McCluskey , Stanford University, USA
pp. 199-204

Using Multiple Expansion Ratios and Dependency Analysis to Improve Test Compression (Abstract)

Richard Putman , Cirrus Logic, Inc., USA; University of Texas, USA
Nur A. Touba , University of Texas, USA
pp. 211-218
Session 6B: Diagnosis II

Accelerating Diagnosis via Dominance Relations between Sets of Faults (Abstract)

Rajsekhar Adapa , Southern Illinois University Carbondale, USA
Spyros Tragoudas , Southern Illinois University Carbondale, USA
Maria K Michael , University of Cyprus
pp. 219-224

Speeding Up Effect-Cause Defect Diagnosis Using a Small Dictionary (Abstract)

Wei Zou , Mentor Graphics Corporation, USA
Wu-Tung Cheng , Mentor Graphics Corporation, USA
Sudhakar M. Reddy , University of Iowa, USA
Huaxing Tang , Mentor Graphics Corporation, USA
pp. 225-230

Using Scan-Dump Values to Improve Functional-Diagnosis Methodology (PDF)

Vishnu C. Vimjam , Virginia Tech, USA
M. Enamul Amyeen , Intel Corporation, USA
Ruifeng Guo , Mentor Graphics Corp., USA
Srikanth Venkataraman , Intel Corporation, USA
Michael Hsiao , Virginia Tech, USA
Kai Yang , Novas Software, USA
pp. 231-238
IP Session 6C: Testing Alone Isn't Enough: Reliability Challenges in Scaled CMOS

Session Abstract (PDF)

pp. 239
Session 7A: Failure Estimation

A UML Based System Level Failure Rate Assessment Technique for SoC Designs (Abstract)

Mohammad Hosseinabady , University of Tehran, Iran
M.H. Neishaburi , University of Tehran, Iran
Pejman Lotfi-Kamran , University of Tehran, Iran
Zainalabedin Navabi , University of Tehran, Iran
pp. 243-248

An Analysis Framework for Transient-Error Tolerance (Abstract)

John P. Hayes , University of Michigan, USA
Ilia Polian , Albert-Ludwigs-University, Germany
Bernd Becker , Albert-Ludwigs-University, Germany
pp. 249-255

Case Study: Soft Error Rate Analysis in Storage Systems (Abstract)

Brian Mullins , Northeastern University, USA
Hossein Asadi , Northeastern University, USA
Mehdi B. Tahoori , Northeastern University, USA
David Kaeli , Northeastern University, USA
Kevin Granlund , EMC Corp. USA
Rudy Bauer , EMC Corp. USA
Scott Romano , EMC Corp. USA
pp. 256-264
Session 7B: Fault Prediction & Evaluation

Silicon Evaluation of Static Alternative Fault Models (Abstract)

Chris Schuermyer , LSI Logic Corporation, USA
Jewel Pangilinan , LSI Logic Corporation, USA
Jay Jahangiri , Mentor Graphics Corporation, USA
Martin Keim , Mentor Graphics Corporation, USA
Janusz Rajski , Mentor Graphics Corporation, USA
Brady Benware , Mentor Graphics Corporation, USA
pp. 265-270

Parameter Estimation for a Model with Both Imperfect Test and Repair (Abstract)

Simon Wilson , Trinity College Dublin, Ireland
Ben Flood , Trinity College Dublin, Ireland
Suresh Goyal , Bell Labs Ireland
Jim Mosher , Lucent Technologies, USA
Susan Bergin , Bell Labs Ireland
Joseph O'Brien , Lucent Technologies, Ireland
Robert Kennedy , Lucent Technologies, Ireland
pp. 271-276

Circuit Failure Prediction and Its Application to Transistor Aging (Abstract)

Mridul Agarwal , Stanford University
Bipul C. Paul , Toshiba Corp.
Ming Zhang , Intel Corporation
Subhasish Mitra , Stanford University
pp. 277-286
IP Session 7C: Open and Highly Extendable Yield Diagnostics Solutions

Session Abstract (PDF)

pp. 287
Session 8A: Analog Test

Transformer-Coupled Loopback Test for Differential Mixed-Signal Specifications (Abstract)

Byoungho Kim , The University of Texas at Austin, USA
Zhenhai Fu , National Semiconductor Corporation, USA
Jacob A. Abraham , The University of Texas at Austin, USA
pp. 291-296

Novel Cross-Loopback Based Test Approach for Specification Test of Multi-Band, Multi-Hardware Radios (Abstract)

V. Natarajan , Georgia Tech, USA
G. Srinivasan , Georgia Tech, USA
A. Chatterjee , Georgia Tech, USA
Craig Force , Texas Instruments, USA
pp. 297-302

Code-Density Test of Analog-to-Digital Converters Using Single Low-Linearity Stimulus Signal (Abstract)

Le Jin , National Semiconductor Corporation, USA
Degang Chen , Iowa State University, USA
Randall Geiger , Iowa State University, USA
pp. 303-310
Session 8B: High Level Test Techniques

High Level Synthesis of Degradable ASICs Using Virtual Binding (Abstract)

N. Honarmand , University of Tehran, Iran
A. Shahabi , University of Tehran, Iran
H. Sohofi , University of Tehran, Iran
M. Abbaspour , Shahid Beheshti University, Iran
Z. Navabi , University of Tehran, Iran
pp. 311-317

Efficient RTL Coverage Metric for Functional Test Selection (Abstract)

Jian Kang , University of Nebraska, USA
Sharad C. Seth , University of Nebraska, USA
Vijay Gangaram , Intel Corporation, USA
pp. 318-324

RTL Test Point Insertion to Reduce Delay Test Volume (PDF)

Kedarnath J. Balakrishnan , NEC Laboratories America, USA
Lei Fang , Virginia Tech, USA
pp. 325-332
IP Session 8C: Impact of New Memory Failure Modes

Session Abstract (PDF)

pp. 333
Special Session 9A: Hot Topic--Fault Tolerant Nanoscale Architectures--The Challenges and Emerging Solutions

Session Abstract (PDF)

pp. 337
Special Session 9B: TTTC 2007 Best Doctoral Thesis Award

Session Abstract (PDF)

pp. 341
Special Session 9C: Hot Topic--Making Analog & Mixed Signal Testing as Robust as Digital

Session Abstract (PDF)

pp. 345
Session 10A: Memory Repair

Multiple Bit Upset Tolerant Memory Using a Selective Cycle Avoidance Based SEC-DED-DAEC Code (Abstract)

Avijit Dutta , University of Texas, Austin, USA
Nur A. Touba , University of Texas, Austin, USA
pp. 349-354

A Built-In Self-Repair Scheme for Multiport RAMs (Abstract)

Tsu-Wei Tseng , National Central University, Taiwan
Chun-Hsien Wu , National Central University, Taiwan
Yu-Jen Huang , National Central University, Taiwan
Jin-Fu Li , National Central University, Taiwan
Alex Pao , Faraday Technology Corporation, Taiwan
Kevin Chiu , Faraday Technology Corporation, Taiwan
Eliot Chen , Faraday Technology Corporation, Taiwan
pp. 355-360

Un-Restored Destructive Write Faults Due to Resistive-Open Defects in the Write Driver of SRAMs (Abstract)

A. Ney , LIRMM, Univeriste de Montpellier II/CNRS, France
P. Girard , LIRMM, Univeriste de Montpellier II/CNRS, France
C. Landrault , LIRMM, Univeriste de Montpellier II/CNRS, France
S. Pravossoudovitch , LIRMM, Univeriste de Montpellier II/CNRS, France
A. Virazel , LIRMM, Univeriste de Montpellier II/CNRS, France
M. Bastian , Infineon Technologies France
pp. 361-368
Session 10B: SOC Test

Using Domain Partitioning in Wrapper Design for IP Cores Under Power Constraints (Abstract)

Thomas Edison Yu , Nara Institute of Science and Technology, Japan
Tomokazu Yoneda , Nara Institute of Science and Technology, Japan
Danella Zhao , University of Louisiana at Lafayette, USA
Hideo Fujiwara , Nara Institute of Science and Technology, Japan
pp. 369-374

Design of Test Access Mechanism for AMBA-Based System-on-a-Chip (Abstract)

Jaehoon Song , Hanyang University, Korea
Piljae Min , Hanyang University, Korea
Hyunbean Yi , Hanyang University, Korea
Sungju Park , Hanyang University, Korea
pp. 375-380

TAM Design and Optimization for Transparency-Based SoC Test (Abstract)

Tomokazu Yoneda , Nara Institute of Science and Technology, Japan
Akiko Shuto , Hiroshima City University, Japan
Hideyuki Ichihara , Hiroshima City University, Japan
Tomoo Inoue , Hiroshima City University, Japan
Hideo Fujiwara , Nara Institute of Science and Technology, Japan
pp. 381-388
Session 11A: RF Test II

A Low Cost Spectral Power Extraction Technique for RF Transceiver Testing (Abstract)

T.-L. Hung , National Taiwan University, Taiwan
J.-L. Huang , National Taiwan University, Taiwan
pp. 389-394

Alternate Diagnostic Testing and Compensation of RF Transmitter Performance Using Response Detection (Abstract)

Rajarajan Senguttuvan , Georgia Institute of Technology, USA
Abhijit Chatterjee , Georgia Institute of Technology, USA
pp. 395-400

A Low-Noise Amplifier with Integrated Current and Power Sensors for RF BIST Applications (Abstract)

Yen-Chih Huang , National Taiwan University, Taiwan
Hsieh-Hung Hsieh , National Taiwan University, Taiwan
Liang-Hung Lu , National Taiwan University, Taiwan
pp. 401-408
Session 11B: Design for Test

Automated Design and Insertion of Optimal One-Hot Bus Encoders (Abstract)

Peter Wohl , Synopsys Inc.
A. Waicukauski , Synopsys Inc.
Sanjay Patel , Synopsys Inc.
pp. 409-415

Transition Fault Testability in Bit Parallel Multipliers over GF(2^{m}) (Abstract)

H. Rahaman , Bengal Engg. & Sci. Univ., India
J. Mathew , University of Bristol, UK
B.K. Sikdar , Bengal Engg. & Sci. Univ., India
D.K. Pradhan , University of Bristol, UK
pp. 422-430
IP Session 11C: Collaborative DFT Practices Needed for Low-Cost Testing

Session Abstract (PDF)

pp. 431-432
Session 12A: Testing Large Chips

DfT for the Reuse of Networks-on-Chip as Test Access Mechanism (Abstract)

Alexandre M. Amory , UFRGS Federal University, Brazil
Frederico Ferlini , PUCRS Catholic University, Brazil
Marcelo Lubaszewski , UFRGS Federal University, Brazil
Fernando Moraes , PUCRS Catholic University, Brazil
pp. 435-440

Novel Approach to Clock Fault Testing for High Performance Microprocessors (Abstract)

C. Metra , Univ. of Bologna, Italy
M. Omana , Univ. of Bologna, Italy
TM Mak , Intel Corporation, USA
S. Tam , Intel Corporation, USA
pp. 441-446

At-Speed Testing of Core-Based System-on-Chip Using an Embedded Micro-Tester (Abstract)

Matthieu Tuna , University Pierre et Marie Curie, LIP6, France
Mounir Benabdenbi , University Pierre et Marie Curie, LIP6, France
Alain Greiner , University Pierre et Marie Curie, LIP6, France
pp. 447-454
Session 12B: Ensuring Secure Chips

VIm-Scan: A Low Overhead Scan Design Approach for Protection of Secret Key in Scan-Based Secure Chips (Abstract)

Somnath Paul , Case Western Reserve University
Rajat Subhra Chakraborty , Case Western Reserve University
Swarup Bhunia , Case Western Reserve University
pp. 455-460

Effects of Embedded Decompression and Compaction Architectures on Side-Channel Attack Resistance (Abstract)

Chunsheng Liu , University of Nebraska-Lincoln, USA
Yu Huang , Mentor Graphics, USA
pp. 461-468
IP Session 12C: Board and System Level Memory Cluster Test Problems and Proposed Solutions

Session Abstract (PDF)

pp. 469
Special Session 13A: New Topic Session--Nano-Electronics will be Asynchronous

Session Abstract (PDF)

pp. 473
Special Session 13B: Hot Topic--Testing in the Presence of NOCs

Session Abstract (PDF)

pp. 477-478
Special Session 13C: Panel--RF Yield: Is it a Problem?

Session Abstract (PDF)

pp. 481
Author Index

Author Index (PDF)

pp. 482
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