The Community for Technology Leaders
2013 IEEE 31st VLSI Test Symposium (VTS) (2006)
Berkeley, California
Apr. 30, 2006 to May 4, 2006
ISBN: 0-7695-2514-8
TABLE OF CONTENTS
Introduction

Organizing Committee (PDF)

pp. xiii-xv

Program Committee (PDF)

pp. xvii

Reviewers (PDF)

pp. xviii

Acknowledgments (PDF)

pp. xix

Awards (PDF)

pp. xxvii-xxix
Session 1A: Delay Testing I

The Impacts of Untestable Defects on Transition Fault Testing (Abstract)

Xijiang Lin , Mentor Graphics Corp.
Janusz Rajski , Mentor Graphics Corp.
pp. 2-7

Low-Cost Scan-Based Delay Testing of Latch-Based Circuits with Time Borrowing (Abstract)

Kun Young Chung , University of Southern California
Sandeep K. Gupta , University of Southern California
pp. 8-15

Path Delay Fault Simulation on Large Industrial Designs (Abstract)

Srinivas Patil , Intel Corporation
Suriyaprakash Natarajan , Intel Corporation
Sreejit Chakravarty , Intel Corporation
pp. 16-23
Session 1B: High Speed Interconnect Test

A Scheme for On-Chip Timing Characterization (Abstract)

Jacob A. Abraham , The University of Texas at Austin
Gary Carpenter , IBM Austin Research Laboratory
Kevin Nowka , IBM Austin Research Laboratory
Ramyanshu Datta , The University of Texas at Austin
pp. 24-29

BIST for Network-on-Chip Interconnect Infrastructures (Abstract)

Andr? Ivanov , University of British Columbia, Canada
Cristian Grecu , University of British Columbia, Canada
Partha Pande , Washington State University
Res Saleh , University of British Columbia, Canada
pp. 30-35

Mixed PLB and Interconnect BIST for FPGAs Without Fault-Free Assumptions (Abstract)

Vishal Suthar , Univ. of Illinois at Chicago
Shantanu Dutt , Univ. of Illinois at Chicago
pp. 36-43
Session 1C - IP Session: Reliability Screening Methods for High-Performance Processors in Advanced Technologies

Session Abstract (PDF)

Phil Nigh , IBM
pp. 44
Session 2A: Heat and Power Issues in Test

Thermal-Aware Testing of Network-on-Chip Using Multiple-Frequency Clocking (Abstract)

Vikram Iyengar , IBM Microelectronics
Chunsheng Liu , University of Nebraska-Lincoln
D.K. Pradhan , University of Bristol, UK
pp. 46-51

PEAKASO: Peak-Temperature Aware Scan-Vector Optimization (Abstract)

Minsik Cho , The University of Texas at Austin
David Z. Pan , The University of Texas at Austin
pp. 52-57

A New ATPG Method for Efficient Capture Power Reduction During Scan Testing (Abstract)

Kewal K. Saluja , University of Wisconsin - Madison
Seiji Kajihara , Kyushu Institute of Technology, Japan
Khader S. Abdel-Hafez , SynTest Technologies
Xiaoqing Wen , Kyushu Institute of Technology, Japan
Kozo Kinoshita , Osaka Gakuin University, Japan
Laung-Terng Wang , SynTest Technologies
Tatsuya Suzuki , Kyushu Institute of Technology, Japan
Kohei Miyase , Japan Science and Technology Agency, Japan
pp. 58-65
Session 2B: Test Quality

Iterative OPDD Based Signal Probability Calculation (Abstract)

Avijit Dutta , University of Texas, Austin
Nur A. Touba , University of Texas, Austin
pp. 72-77

Silicon Evaluation of Logic Proximity Bridge Patterns (Abstract)

Eric N Tran , Intel Corporation
Vishwashanth Kasulasrinivas , Intel Corporation
Sreejit Chakravarty , Intel Corporation
pp. 78-85
Session 2C - IP Session: Scan Compression: Techniques, Tradeoffs and Entitlement

Session Abstract (PDF)

Rubin A. Parekhji , Texas Instruments, Ltd., India
pp. 86-87
Session 3A: IP Protection and Interconnect Testing

Upper Bounding Fault Coverage by Structural Analysis and Signal Monitoring (Abstract)

Soumitra Bose , Intel Corporation
Vijay Gangaram , Intel Corporation
Vishwani D. Agrawal , Auburn University
pp. 88-93

A Low-Cost Solution for Protecting IPs Against Scan-Based Side-Channel Attacks (Abstract)

Jeremy Lee , University of Maryland Baltimore County
Jim Plusquellic , University of Maryland Baltimore County
Mohammad Tehranipoor , University of Maryland Baltimore County
pp. 94-99

Interconnect Testing for Networks on Chips (Abstract)

Spyros Tragoudas , Southern Illinois University
Khadija Stewart , Southern Illinois University
pp. 100-107
Session 3B: Flash and Memory Testing

An Overview of Failure Mechanisms in Embedded Flash Memories (Abstract)

J.-M. Daga , ATMEL Rousset, France
P. Girard , Universit? de Montpellier, France
M. Combe , ATMEL Rousset, France
A. Virazel , Universit? de Montpellier, France
C. Landrault , Universit? de Montpellier, France
O. Ginez , ATMEL Rousset, France
S. Pravossoudovitch , Universit? de Montpellier, France
pp. 108-113

A Built-In Self-Repair Scheme for NOR-Type Flash Memory (Abstract)

Chao-Hsun Chen , National Tsing Hua University, Taiwan
Cheng-Wen Wu , National Tsing Hua University, Taiwan
Yu-Ying Hsiao , National Tsing Hua University, Taiwan
pp. 114-119

Minimal March Test Algorithm for Detection of Linked Static Faults in Random Access Memories (Abstract)

G. Harutunyan , Virage Logic, Armenia
Y. Zorian Zorian , Virage Logic, Armenia
V.A. Vardanian , Virage Logic, Armenia
pp. 120-127
Session 3C - IP Session: Nanometer IC Testing: Perspective from Foundries

Session Abstract (PDF)

Cheng-Wen Wu , National Tsing Hua University
pp. 128-129
Session 4A: Yield Analysis

An Error-Oriented Test Methodology to Improve Yield with Error-Tolerance (Abstract)

Melvin A. Breuer , University of Southern California
Kuen-Jong Lee , National Cheng Kung University, Taiwan
Tong-Yu Hsieh , National Cheng Kung University, Taiwan
pp. 130-135

BIST Pretest of ICs: Risks and Benefits (Abstract)

Yoshiyuki Nakamura , Nara Institute of Science and Technology, Japan
Hideo Fujiwara , Nara Institute of Science and Technology, Japan
Jacob Savir , New Jersey Institute of Technology
pp. 142-149
Session 4B - New Topic Session: Emerging Nanoelectronic Devices for High-Speed, Low-Power Applications

Session Abstract (PDF)

Bernard Courtois , TIMA-France
pp. 150-151
Session 4C - IP Session: TRP in Action: Embedded Instrumentation in FPGAs

Session Abstract (PDF)

Ajay Khoche , Agilent Technologies
pp. 152-153
Session 5A: - Special Session: The Future of DFT Sector: Point Tools or Integrated Solutions

Session Abstract (PDF)

Dennis Wassung , Canaccord Adams
Yervant Zorian , Virage Logic
pp. 154-155
Session 5B - Special Session: Elevator Talks

Session Abstract (PDF)

Erik Chmelar , LSI Logic
Edward J. McCluskey , Stanford University
pp. 156-157
Session 5C - Embedded Tutorial: Functional ATPG

Session Abstract (PDF)

Praveen Parvathala , Intel Corporation
pp. 158-159
Session 6A: Test Generation and Test Flows

Improved Handling of False and Multicycle Paths in ATPG (Abstract)

Vlado Vorisek , Freescale Semiconductor
Bruce Swanson , Mentor Graphics Corporation
Kun-Han Tsai , Mentor Graphics Corporation
Dhiraj Goswami , Mentor Graphics Corporation
pp. 160-165

On the Automation of the Test Flow of Complex SoCs (Abstract)

D. Appello , STMicroelectronics - Agrate Brianza (MI), Italy
P. Bernardi , Politecnico di Torino, Italy
M. Grosso , Politecnico di Torino, Italy
V. Tancorre , STMicroelectronics - Agrate Brianza (MI), Italy
M. Rebaudengo , Politecnico di Torino, Italy
M. Sonza Reorda , Politecnico di Torino, Italy
pp. 166-171

Improving Gate-Level ATPG by Traversing Concurrent EFSMs (Abstract)

Giuseppe Di Guglielmo , Universita di Verona, Italy
Cristina Marconcini , Universita di Verona, Italy
Franco Fummi , Universita di Verona, Italy
Graziano Pravadelli , Universita di Verona, Italy
pp. 172-179
Session 6B: IDDQ, MEMS, and Wireless Testing

X-IDDQ: A Novel Defect Detection Technique Using IDDQ Data (Abstract)

Anura P. Jayasumana , Colorado State University
Yashwant K. Malaiya , Colorado State University
Ashutosh Sharma , Colorado State University
pp. 180-185

Energy Efficient Software-Based Self-Test for Wireless Sensor Network Nodes (Abstract)

Rong Zhang , McGill University, Canada
Katarzyna Radecka , Concordia University, Canada
Zeljko Zilic , McGill University, Canada
pp. 186-191

Alternate Electrical Tests for Extracting Mechanical Parameters of MEMS Accelerometer Sensors (Abstract)

Vishwanath Natarajan , Georgia Intitute of Technology
Abhijit Chatterjee , Georgia Institute of Technology
Soumendu Bhattacharya , Georgia Institute of Technology
pp. 192-199
Session 6C - IP Session: Test Strategies of Leading Edge SoCs

Session Abstract (PDF)

Kazumi Hatayama , Renesas Technology Corp.
pp. 200-201
Session 7A: Designing Robust CMOS and Nanoelectronics

Design Optimization for Robustness to Single Event Upsets (Abstract)

Kartik Mohanram , Rice University
Mihir R. Choudhury , Rice University
Quming Zhou , Rice University
pp. 202-207

Design of Soft Error Resilient Linear Digital Filters Using Checksum-Based Probabilistic Error Correction (Abstract)

Soumendu Bhattacharya , Georgia Institute of Technology
Maryam Ashouei , Georgia Institute of Technology
Abhijit Chatterj , Georgia Institute of Technology
pp. 208-213
Session 7B: RF Testing

RF Front-end System Gain and Linearity Built-in Test (Abstract)

Mani Soma , University of Washington
Qi Wang , University of Washington
pp. 228-233

Integrated CMOS Power Sensors for RF BIST Applications (Abstract)

Hsieh-Hung Hsieh , National Taiwan University, Taiwan
Liang-Hung Lu , National Taiwan University, Taiwan
pp. 234-239
Session 7C - IP Sessin: High Test Parallelism, Throughput and Quality at a Low Cost: Which Test Cells and Which Partitioning of Test Resources Can Enable All This?

Session Abstract (PDF)

Davide Appello , STMicroelectronics, Italy
pp. 240-241
Session 8A: Test Size Reductions

Modular Compactor of Test Responses (Abstract)

Wojciech Rajski , Oregon State University
Janusz Rajski , *Mentor Graphics Corporation
pp. 242-251
Session 8B: Transistor Level Diagnosis

A Gate-Level Method for Transistor-Level Bridging Fault Diagnosis (Abstract)

Will Moore , Oxford University
Guido Gronthoud , Philips Research Labs
Xinyue Fan , Oxford University, UK
Mario Konijnenburg , Philips Research Labs
Camelia Hora , Philips Research Labs
pp. 266-271

Parametric Fault Diagnosis for Analog Circuits Using a Bayesian Framework (Abstract)

Sule Ozev , Duke University
Fang Liu , Duke University
Plamen K. Nikolov , Duke University
pp. 272-277

Decision Tree Based Mismatch Diagnosis in Analog Circuits (Abstract)

Hosam Haggag , National Semiconductor
Mingjing Chen , UC San Diego
Alex Orailoglu , UC San Diego
pp. 278-285
Session 8C - IP Session: Soft Error Impact on Modern Systems

Session Abstract (PDF)

Michael Nicolaidis , TIMA Labs & iRoC Technologies
pp. 286-287
Session 9A - Panel Session: Real-Time Volume Diagnostics: Requirements and Challenges

Session Abstract (PDF)

Peter Muhmenthaler , Infineon Technologies
Ajay Khoche , Semiconductor Test Solutions, Agilent Technologies
pp. 288-289
Session 9B - Special Sesion: Doctoral Thesis Award

Session Abstract (PDF)

Andreas Veneris , University of Toronto
Yiorgos Makris , Yale University
pp. 290-291
Session 9C - Panel Session: Three Questions to Oracle

Session Abstract (PDF)

Kee Sup Kim , Intel
pp. 292-293
Session 10A: Delay Testing II

Robust Test Generation for Precise Crosstalk-induced Path Delay Faults (Abstract)

Peifu Shen , Beijing Normal University, China
Xiaowei Li , Chinese Academy of Sciences, China
Huawei Li , Chinese Academy of Sciences, China
pp. 300-305

Multi-Cycle Sensitizable Transition Delay Faults (Abstract)

Jais Abraham , Texas Instruments, India
Arun Kumar , Texas Instruments, India
Uday Goel , Indian Institute of Technology, India
pp. 306-313
Session 10B: Analog Test

A SNDR BIST for \Sigma\Delta Analogue-to-Digital Converters (Abstract)

Jean-Louis Carbon?ro , STMicroelectronics, France
Ahc?ne Bounceur , TIMA Laboratory, France
Luis Rol?ndez , TIMA Laboratory, France
Salvador Mir , TIMA Laboratory, France
pp. 314-319

Investigating the Efficiency of Integrator-Based Capacitor Array Testing Techniques (Abstract)

Sai Raghuram Durbha , Southern Illinois University
Amit Laknaur , Southern Illinois University
Haibo Wang , Southern Illinois University
pp. 320-325

Functional Test of Field Programmable Analog Arrays (Abstract)

M. Renovell , Universit? de Montpellier II, France
J.V. Calvano , Instituto de Pesquisas da Marinha do Brasil, Brazil
M. S. Lubaszewski , Universidade Federal do Rio Grande do Sul, Brazil
T. R. Balen , Universidade Federal do Rio Grande do Sul, Brazil
pp. 326-333
Session 10C - IP Session: System-in-Package Design and Test Practices

Session Abstract (PDF)

Bruce Kim , University of Alabama
Yervant Zorian , Virage Logic
pp. 334-335
Session 11A: Delay Testing III

Enhanced Timing-Based Transition Delay Testing for Small Delay Defects (Abstract)

Richard Putman , Cirrus Logic, Inc.
Rahul Gawde , Cirrus Logic, Inc.
pp. 336-342

Scan Tests with Multiple Fault Activation Cycles for Delay Faults (Abstract)

Xijiang Lin , Mentor Graphics Corp.
Zhuo Zhang , University of Iowa
Sudhakar M. Reddy , University of Iowa
Janusz Rajski , Mentor Graphics Corp.
Irith Pomeranz , Purdue University
pp. 343-348
Session 11B: Nanoscale Testing

Low V_D_D vs. Delay: Is it Really a Good Correlation Metric for Nanometer ICs? (Abstract)

J. Segura , Universitat de les Illes Balears, Spain
S.A. Bota, , Universitat de les Illes Balears. Spain
J.L. Rossell? , Universitat de les Illes Balears. Spain
M. Rosales , Universitat de les Illes Balears. Spain
pp. 358-363

Exploiting Regularity for Inductive Fault Analysis (Abstract)

Jason G. Brown , Carnegie Mellon University
R. D. (Shawn) Blanton , Carnegie Mellon University
pp. 364-369

SCT: An Approach For Testing and Configuring Nanoscale Devices (Abstract)

Mohammad Tehranipoor , University of Maryland Baltimore County
Reza M.P. Rad , University of Maryland Baltimore County
pp. 370-377
Session 11C - IP Session: Impact of Variations on Designs and Test

Session Abstract (PDF)

James Tschanz , Intel Corporation
pp. 378-379
Session 12A: Scan Based Diagnosis

A Pattern Ordering Algorithm for Reducing the Size of Fault Dictionaries (Abstract)

M. Grosso , Politecnico di Torino, Italy
P. Bernardi , Politecnico di Torino, Italy
M. Sonza Reorda , Politecnico di Torino, Italy
M. Rebaudengo , Politecnico di Torino, Italy
pp. 386-391

Dominance Based Analysis for Large Volume Production Fail Diagnosis (Abstract)

S. Venkataraman , Intel Corporation
B. Seshadri , Purdue University
M.E. Amyeen , Intel Corporation
S.M. Reddy , University of Iowa
I. Pomeranz , Purdue University
pp. 392-399
Session 12B: Mixed Signal Test

A Period Tracking Based On-Chip Sinusoidal Jitter Extraction Technique (Abstract)

J.-L. Huang , National Taiwan University, Taiwan
C.-Y. Kuo , National Taiwan University, Taiwan
pp. 400-405

Spectral Prediction for Specification-Based Loopback Test of Embedded Mixed-Signal Circuits (Abstract)

Hongjoong Shin , The University of Texas at Austin
Jacob A. Abraham , The University of Texas at Austin
Byoungho Kim , The University of Texas at Austin
pp. 412-419
Session 13A: Embedded Tutorial: Silicon Debug Challenges for Nanometer Designs

Session Abstract (PDF)

Bob Gottlieb , Intel Corporation
Rajesh Galivanche , Intel Corporation
pp. 422-423
Session 13B - Hot Topic Session: Signal Integrity: How Can It be Designed into Multiprocessor Platforms, Systems On-Chip, and Systems in-Package?

Session Abstract (PDF)

Andr? Ivanov , University of British Columbia
pp. 424-425
Session 13C - Panel Session: Changing Role of Test: Is ATE Ready?

Session Abstract (PDF)

Pete O?Neil , Avago Technologies
Mike Rodgers , Intel Corporation
Ajay Khoche , Semiconductor Test Solutions, Agilent Technologies
pp. 426
Author Index

Author Index (PDF)

pp. 427-428
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