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23rd IEEE VLSI Test Symposium (VTS'05) (2005)
Palm Springs, California
May 1, 2005 to May 5, 2005
ISSN: 1093-0167
ISBN: 0-7695-2314-5
4C: IP Session - High Speed I/O Test
4B: IP Session - Adaptive Test
7C: IP Session: Embedded Memory Test & Repair Drives Higher Yield in Nanometer Technologies
8C: IP Session - Test Resource Partitioning in Action
9A: Embedded Tutorial: Test with Variations - How Much Can Be Solved in the Design Process?
9C: Panel Session - Are DFT and Manufacturing Test Good Boosts for DFM?
10C: IP Session - SoC Test Practices in Japan
3C: IP Session - Soft Errors
13A: Panel Session - IEEE 1500: Embedded Core-Based Test Standard: Why Should I Adopt It?
13B: Hot Topic Session - Test and DFM: Managing Yield at 90nm and below
13C: Panel Session - Analog TRP: Is Convergence on Horizon?
2C: IP Session - DFT for SoCs in Wireless Applications
11C: IP Session - Delay Fault Testing: Industrial Case Studies
12C: IP Session - On the Way from DFT to DFM...Looking for Systematic Marginalities

Foreword (PDF)

pp. xi

Organizing Committee (PDF)

pp. xii-xiii
Plenary Session

Welcome Address (PDF)

pp. null

Keynote Address (PDF)

pp. null

Invited Address (PDF)

pp. null
1A: Memory BIST

Flash Memory Built-In Self-Diagnosis with Test Mode Control (Abstract)

Jen-Chieh Yeh , National Tsing Hua University
Yan-Ting Lai , National Tsing Hua University
Yuan-Yuan Shih , National Tsing Hua University
Cheng-Wen Wu , National Tsing Hua University
Chien-Hung Ho , eMemory Technology Inc.
Yen-Tai Lin , eMemory Technology Inc.
pp. 15-20
1B: Delay Testing I

Transition Tests for High Performance Microprocessors (Abstract)

Yi-Shing Chang , Intel Corporation
Sreejit Chakravarty , Intel Corporation
Hiep Hoang , Intel Corporation
Nick Thorpe , Intel Corporation
Khen Wee , Intel Corporation
pp. 29-34

On Silicon-Based Speed Path Identification (Abstract)

Leonard Lee , University of California at Santa Barbara
Li-C. Wang , University of California at Santa Barbara
Praveen Parvathala , Intel Corporation
T. M. Mak , Intel Corporation
pp. 35-41

At-Speed Transition Fault Testing With Low Speed Scan Enable (Abstract)

Nisar Ahmed , Texas Instruments India
C. P. Ravikumar , Texas Instruments India
Mohammad Tehranipoor , Texas Instruments India
Jim Plusquellic , Texas Instruments India
pp. 42-47
2A: Memory Testing I

Modeling and Testing Comparison Faults for Ternary Content Addressable Memories (Abstract)

Jin-Fu Li , National Central University
Chou-Kun Lin , National Central University
pp. 60-65

SRAM Retention Testing: Zero Incremental Time Integration with March Algorithms (Abstract)

Baosheng Wang , University of British Columbia
Yuejian Wu , Nortel Networks
Josh Yang , University of British Columbia
Andr? Ivanov , University of British Columbia
Yervant Zorian , Virage Logic Corporation
pp. 66-71
2B: High-Speed Testing and Clock Skew Compensation

Meeting the Test Challenges of the 1 Gbps Parallel RapidIO? Interface with New Automatic Test Equipment Capabilities (Abstract)

Darren Aaberge , Freescale Semiconductor, Inc.
Ken Mockler , Freescale Semiconductor, Inc.
Dieu Van Dinh , Freescale Semiconductor, Inc.
Raoul Belleau , Teradyne, Inc.
Tim Donovan , Teradyne, Inc.
Reid Hewlitt , Teradyne, Inc.
pp. 75-84

Cantilever Type Probe Card for At-Speed Memory Test on Wafer (Abstract)

Hitoshi Iwai , Toshiba Corporation Semiconductor Company
Atsushi Nakayama , Toshiba Corporation Semiconductor Company
Naoko Itoga , Toshiba Corporation Semiconductor Company
Kotaro Omata , Apex Inc.
pp. 85-89

Low Cost Scheme for On-Line Clock Skew Compensation (Abstract)

Martin Omaña , University of Bologna
Daniele Rossi , University of Bologna
Cecilia Metra , University of Bologna
pp. 90-95
3A: Test Data Compression and Self-Test

Implementing a Scheme for External Deterministic Self-Test (Abstract)

Abdul Wahid Hakmi , Universit?t Stuttgart
Hans-Joachim Wunderlich , Universit?t Stuttgart
Valentin Gherman , Universit?t Stuttgart
Michael Garbers , Philips Semiconductors GmbH
J? Schl?ffel , Philips Semiconductors GmbH
pp. 101-106

On A Software-Based Self-Test Methodology and Its Application (Abstract)

Charles H.-P. Wen , University of California at Santa Barbara
Li-C. Wang , University of California at Santa Barbara
Kwang-Ting Cheng , University of California at Santa Barbara
Kai Yang , University of California at Santa Barbara
Wei-Ting Liu , Industrial Technology Research Institute
Ji-Jan Chen , Industrial Technology Research Institute
pp. 107-113

Synthesis of X-Tolerant Convolutional Compactors (Abstract)

Janusz Rajski , Mentor Graphics Corporation
Jerzy Tyszer , Poznan University of Technology
pp. 114-119
3B: Analog Testing I

An Efficient Random Jitter Measurement Technique Using Fast Comparator Sampling (Abstract)

Dongwoo Hong , University of California at Santa Barbara
Cameron Dryden , Metrologic Instruments
Gordon Saksena , Teradyne Corp.
pp. 123-130

On-Chip Spectrum Analyzer for Analog Built-In Self Test (Abstract)

Anup P. Jose , Columbia University
Keith A. Jenkins , IBM T.J. Watson Research Center
Scott K. Reynolds , IBM T.J. Watson Research Center
pp. 131-136
4A: Defect-Oriented Testing

Towards an Understanding of No Trouble Found Devices (Abstract)

Scott Davidson , Sun Microsystems, Inc.
pp. 147-152

Reducing Pattern Delay Variations for Screening Frequency Dependent Defects (Abstract)

Benjamin N Lee , University of Califoria at Santa Barbara
Li-C. Wang , University of Califoria at Santa Barbara
Magdy S. Abadir , Freescale Semiconductor
pp. 153-160

Effective TARO Pattern Generation (Abstract)

Intaik Park , Stanford University
Ahmad Al-Yamani , Stanford University and LSI Logic Corporation
Edward J. McCluskey , Stanford University
pp. 161-166
5B: Emerging Technologies - Reliable and Fault-Tolerant Wireless Sensor Networks

Abstract (PDF)

pp. 173
6A: Memory Testing II

A New Algorithm for Dynamic Faults Detection in RAMs (Abstract)

Mohamed Azimane , Philips Research
Ananta Majhi , Philips Research
Guido Gronthoud , Philips Research
Maurice Loousberg , Philips Research
pp. 177-182

Data Retention Fault in SRAM Memories: Analysis and Detection Procedures (Abstract)

Luigi Dilillo , Universit? de Montpellier II / CNRS
Patrick Girard , Universit? de Montpellier II / CNRS
Serge Pravossoudovitch , Universit? de Montpellier II / CNRS
Arnaud Virazel , Universit? de Montpellier II / CNRS
Magali Bastian Hage-Hassan , Infineon Technologies France
pp. 183-188

Test and Characterization of a Variable-Capacity Multilevel DRAM (Abstract)

John C. Koob , University of Alberta
Sue A. Ung , University of Alberta
Ashwin S. Rao , University of Alberta
Daniel A. Leder , University of Alberta
Craig S. Joly , University of Alberta
Kristopher C. Breen , University of Alberta
Tyler Brandon , University of Alberta
Michael Hume , University of Alberta
Bruce F. Cockburn , University of Alberta
Duncan G. Elliott , University of Alberta
pp. 189-197
6B: FPGA & MEMS Testing

A BIST Scheme for FPGA Interconnect Delay Faults (Abstract)

Chun-Chieh Wang , National Tsing Hua University
Jing-Jia Liou , National Tsing Hua University
Yen-Lin Peng , National Tsing Hua University
Chih-Tsun Huang , National Tsing Hua University
Cheng-Wen Wu , National Tsing Hua University
pp. 201-206

Soft Error Mitigation for SRAM-Based FPGAs (Abstract)

Ghazanfar-Hossein Asadi , Northeastern University
Mehdi Baradaran Tahoori , Northeastern University
pp. 207-212

On-Chip Electro-Thermal Stimulus Generation for a MEMS-Based Magnetic Field Sensor (Abstract)

N. Dumas , Universite Montpellier II/CNRS
F. Aza? , Universite Montpellier II/CNRS
L. Latorre , Universite Montpellier II/CNRS
P. Nouet , Universite Montpellier II/CNRS
pp. 213-218
7A: Delay Testing II

Measures to Improve Delay Fault Testing on Low-Cost Testers - A Case Study (Abstract)

Matthias Beck , Infineon Technologies AG
Olivier Barondeau , Infineon Technologies AG
Frank Poehl , Infineon Technologies AG
Xijiang Lin , Mentor Graphics Corporation
Ron Press , Mentor Graphics Corporation
pp. 223-228

Pseudo-Functional Scan-based BIST for Delay Fault (Abstract)

Yung-Chieh Lin , University of California at Santa Barbara
Feng Lu , University of California at Santa Barbara
Kwang-Ting Cheng , University of California at Santa Barbara
pp. 229-234

Static Compaction of Delay Tests Considering Power Supply Noise (Abstract)

Jing Wang , Texas A&M University
Xiang Lu , Texas A&M University
Wangqi Qiu , Texas A&M University
Ziding Yue , Texas A&M University
Steve Fancler , Texas A&M University
Weiping Shi , Texas A&M University
D. M. H. Walker , Texas A&M University
pp. 235-240
7B: RF Testing

Built-In Test of RF Components Using Mapped Feature Extraction Sensors (Abstract)

S. Sermet Akbay , Georgia Institute of Technology
Abhijit Chatterjee , Georgia Institute of Technology
pp. 243-248

A CMOS RF RMS Detector for Built-in Testing of Wireless Transceivers (Abstract)

Alberto Valdes-Garcia , Texas A&M University
Radhika Venkatasubramanian , Texas A&M University
Rangakrishnan Srinivasan , Texas A&M University
Jose Silva-Martinez , Texas A&M University
Edgar S?nchez-Sinencio , Texas A&M University
pp. 249-254

Low-Cost Alternate EVM Test for Wireless Receiver Systems (Abstract)

Achintya Halder , Georgia Institute of Technology
Abhijit Chatterjee , Georgia Institute of Technology
pp. 255-260
8A: Low-Power Testing

On Low-Capture-Power Test Generation for Scan Testing (Abstract)

Xiaoqing Wen , Kyushu Institute of Technology
Yoshiyuki Yamashita , Kyushu Institute of Technology
Seiji Kajihara , Kyushu Institute of Technology
Laung-Terng Wang , SynTest Technologies, Inc.
Kewal K. Saluja , University of Wisconsin - Madison
Kozo Kinoshita , Osaka Gakuin University
pp. 265-270

Reduction of Instantaneous Power by Ripple Scan Clocking (Abstract)

Kirti Joshi , University of Texas at El Paso
Eric MacDonald , University of Texas at El Paso
pp. 271-276

Jump Scan: A DFT Technique for Low Power Testing (Abstract)

Min-Hao Chiu , National Taiwan University
James C.-M. Li , National Taiwan University
pp. 277-282
8B: Nanometer and Circuit-Level Effects

Modeling and Testing of SRAM for New Failure Mechanisms Due to Process Variations in Nanoscale CMOS (Abstract)

Qikai Chen , Purdue University
Hamid Mahmoodi , Purdue University
Swarup Bhunia , Purdue University
Kaushik Roy , Purdue University
pp. 292-297

Design of Adaptive Nanometer Digital Systems for Effective Control of Soft Error Tolerance (Abstract)

Abdulkadir U. Diril , Georgia Institute of Technology
Yuvraj S. Dhillon , Georgia Institute of Technology
Abhijit Chatterjee , Georgia Institute of Technology
Adit D. Singh , Auburn University
pp. 298-303
10A: Reliability

Synthesis of Low Power CED Circuits Based on Parity Codes (Abstract)

Shalini Ghosh , University of Texas at Austin
Sugato Basu , University of Texas at Austin
Nur A. Touba , University of Texas at Austin
pp. 315-320
10B: Testing of Bridging Faults and Test Scheduling

Experimental Evaluation of Bridge Patterns for a High Performance Microprocessor (Abstract)

Sreejit Chakravarty , Intel Corporation
YiShing Chang , Intel Corporation
Hiep Hoang , Intel Corporation
Sridhar Jayaraman , Intel Corporation
Silvio Picano , Intel Corporation
Cheryl Prunty , Intel Corporation
Eric W Savage , Intel Corporation
Rehan Sheikh , Intel Corporation
Eric N. Tran , Intel Corporation
Khen Wee , Intel Corporation
pp. 337-342

Resistive Bridge Fault Model Evolution from Conventional to Ultra Deep Submicron Technologies (Abstract)

Ilia Polian , Albert-Ludwigs-University
Sandip Kundu , Intel Corp.
Jean-Marc Galliere , LIRMM - UMII
Piet Engelke , Albert-Ludwigs-University
Michel Renovell , LIRMM - UMII
Bernd Becker , Albert-Ludwigs-University
pp. 343-348

Power-Aware Test Scheduling in Network-on-Chip Using Variable-Rate On-Chip Clocking (Abstract)

Chunsheng Liu , University of Nebraska-Lincoln
Vikram Iyengar , IBM Microelectronics
Jiangfan Shi , University of Nebraska-Lincoln
Erika Cota , Universidade Federal do Rio Grande do Sul
pp. 349-354
11A: Diagnosis

Hierarchical Compactor Design for Diagnosis in Deterministic Logic BIST (Abstract)

Peter Wohl , Synopsys Inc.
John A. Waicukauski , Synopsys Inc.
Sanjay Patel , Synopsys Inc.
Cy Hay , Synopsys Inc.
Emil Gizdarski , Synopsys Inc.
Ben Mathew , Synopsys Inc.
pp. 359-365

Diagnosis of Arbitrary Defects Using Neighborhood Function Extraction (Abstract)

Rao Desineni , Carnegie Mellon University
R. D. (Shawn) Blanton , Carnegie Mellon University
pp. 366-373
11B: Analog Testing II

Testing the Interconnect Networks and I/O Resources of Field Programmable Analog Arrays (Abstract)

Gustavo Pereira , University Federal do Rio Grande do Sul
Antonio Andrade Jr. , University Federal do Rio Grande do Sul
Tiago R. Balen , University Federal do Rio Grande do Sul
Marcelo Lubaszewski , Universidad Federal do Rio Grande do Sul and Universidad de Sevilla
Florence Aza? , Universit? de Montpellier II
Michel Renovell , Universit? de Montpellier II
pp. 389-394
12A: Design-for-Testability

Segmented Addressable Scan Architecture (Abstract)

Ahmad Al-Yamani , LSI Logic Corporation
Erik Chmelar , LSI Logic Corporation
Mikhail Grinchuck , LSI Logic Corporation
pp. 405-411

An Economic Selecting Model for DFT Strategies (Abstract)

Yu-Ting Lin , University of Texas at Austin
Tony Ambler , University of Texas at Austin
pp. 412-417
12B: I_DDQ Testing and Power Supply Noise Analysis

Defect Screening Using Independent Component Analysis on I_DDQ (Abstract)

Ritesh Turakhia , Portland State University
Brady Benware , LSI Logic
Robert Madge , LSI Logic
Thaddeus Shannon , Portland State University
Robert Daasch , Portland State University
pp. 427-432

Hardware Results Demonstrating Defect Detection Using Power Supply Signal Measurements (Abstract)

Dhruva Acharyya , University of Maryland at Baltimore County
Jim Plusquellic , University of Maryland at Baltimore County
pp. 433-438

Pattern Generation and Estimation for Power Supply Noise Analysis (Abstract)

Mehrdad Nourani , University of Texas at Dallas
Mohammad Tehranipoor , University of Maryland at Baltimore County,
Nisar Ahmed , Texas Instruments
pp. 439-444
Author Index

Author Index (PDF)

pp. 453-455
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