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2013 IEEE 31st VLSI Test Symposium (VTS) (2004)
Napa Valley, California
Apr. 25, 2004 to Apr. 29, 2004
ISSN: 1093-0167
ISBN: 0-7695-2134-7
TABLE OF CONTENTS

Foreword (PDF)

pp. xii

Reviewers (PDF)

pp. xvii

Acknowledgements (PDF)

pp. xix
Plenary Session

Keynote Address (PDF)

pp. null

Invited Address (PDF)

pp. null
1A: Paper Session - Defect-Oriented Testing

Excitation, Observation, and ELF-MD: Optimization Criteria for High Quality Test Sets (Abstract)

Amy Wang , Texas A&M University
David Dorsey , Texas A&M University
M. Ray Mercer , Texas A&M University
Jennifer Dworak , Texas A&M University
pp. 9

ELF-Murphy Data on Defects and Test Sets (Abstract)

E. J. McCluskey , Stanford Center for Reliable Computing
Francois-Fabien Ferhani , Stanford Center for Reliable Computing
James C.-M Li , Stanford Center for Reliable Computing
Ahmad Al-Yamani , Stanford Center for Reliable Computing
Chao-Wen Tseng , Stanford Center for Reliable Computing
Edward Li , Stanford Center for Reliable Computing
Subhasish Mitra , Stanford Center for Reliable Computing
Erik Volkerink , Stanford Center for Reliable Computing
pp. 16

An Experimental Study of N-Detect Scan ATPG Patterns on a Processor (Abstract)

Ajay Ojha , Intel Corporation, Hillsboro, OR
Sangbong Lee , Intel Corporation, Hillsboro, OR
Enamul Amyeen , Intel Corporation, Hillsboro, OR
Srikanth Venkataraman , Intel Corporation, Hillsboro, OR
Srihari Sivaraj , Intel Corporation, Hillsboro, OR
Ruifeng Guo , Intel Corporation, Hillsboro, OR
pp. 23
1B: Paper Session - Delay Testing

What Does Robust Testing a Subset of Paths, Tell us about the Untested Paths in the Circuit? (Abstract)

Janak H. Patel , University of Illinois at Urbana Champaign
Manish Sharma , University of Illinois at Urbana Champaign
pp. 31

A Statistical Fault Coverage Metric for Realistic Path Delay Faults (Abstract)

Xiang Lu , Texas A&M University, College Station
Zhuo Li , Texas A&M University, College Station
D. M. H. Walker , Texas A&M University, College Station
Wangqi Qiu , Texas A&M University, College Station
Weiping Shi , Texas A&M University, College Station
Jing Wang , Texas A&M University, College Station
pp. 37

Delay Defect Screening using Process Monitor Structures (Abstract)

Stefan Eichenberger , Philips Semiconductors, Nijmegen, The Netherlands
Erik Volkerink , Stanford University, CA
Subhasish Mitra , Intel Corporating, Sacramento, CA; Stanford University, CA
Edward J. McCluskey , Stanford University, CA
pp. 43
1C: Innovative Practices Session - Silicon Debug and Diagnosis

Scan Dump Tracer (PDF)

pp. null
2A: Paper Session - Current Based Testing

Built-in Current Sensor for ∆I{DDQ} Testing of Deep Submicron Digital CMOS ICs (Abstract)

Josep Rius V?zquez , Universitat Polit?cnica de Catalunya, Spain
Jos? Pineda de Gyvez , Philips Research Laboratories, The Netherlands
pp. 53

On New Current Signatures and Adaptive Test Technique Combination (Abstract)

C. Thibeault , Ecole de technologie superieure, Montreal, Canada
pp. 59

On Comparison of NCR Effectiveness with a Reduced I{DDQ} Vector Set (Abstract)

Sagar Sabade , Texas A&M University, College Station
D. M. H. Walker , Texas A&M University, College Station
pp. 65
2B: Paper Session - Test Data Compression and Low-Speed ATE

Changing the Scan Enable during Shift (Abstract)

Samitha Samaranayake , Massachusetts Institute of Technology, Cambridge, MA
T. W. Williams , Synopsys Inc., Mountain View, CA
Nodari Sitchinava , Synopsys Inc., Mountain View, CA
Emil Gizdarski , Synopsys Inc., Mountain View, CA
Rohit Kapur , Synopsys Inc., Mountain View, CA
Fredric Neuveux , Synopsys Inc., Mountain View, CA
pp. 73

3-Stage Variable Length Continuous-Flow Scan Vector Decompression Scheme (Abstract)

Nur A. Touba , University of Texas, Austin
C. V. Krishna , University of Texas, Austin
pp. 79

Generating At-Speed Array Fail Maps with Low-Speed ATE (Abstract)

Michael Nelms , IBM Microelectronics Division, Essex Junction, VT
Darren Anand , IBM Microelectronics Division, Essex Junction, VT
Kevin Gorman , IBM Microelectronics Division, Essex Junction, VT
pp. 87
2C: Innovative Practices Session - Practical Experience with Test and Repair of Large Memory Systems
3A: Paper Session - Pattern Debug, Yield Analysis and FPGA Testing

Razor: A Tool for Post-Silicon Scan ATPG Pattern Debug and Its Application (Abstract)

Srikanth Venkataraman , Intel Corporation, Hillsboro, OR
Debashis Nayak , Intel Corporation, Hillsboro, OR
Paul Thadikaran , Intel Corporation, Hillsboro, OR
pp. 97

Yield Analysis of Logic Circuits (Abstract)

B. Mathew , Synopsys Inc., Mountain View, CA
K. Giarda , ST Microelectronics, Cornaredo, Italy
E. Gizdarski , Synopsys Inc., Mountain View, CA
V. Tancorre , ST Microelectronics, Cornaredo, Italy
D. Appello , ST Microelectronics, Cornaredo, Italy
A. Fudoli , ST Microelectronics, Cornaredo, Italy
pp. 103
3B: Paper Session - Memory Testing I

Effects of Bit Line Coupling on the Faulty Behavior of DRAMs (Abstract)

Ad J. van de Goor , Delft University of Technology, The Netherlands
Said Hamdioui , Delft University of Technology, The Netherlands
Zaid Al-Ars , Delft University of Technology, The Netherlands
pp. 117

New Test Methodology for Resistive Open Defect Detection in Memory Address Decoders (Abstract)

Ananta K. Majhi , Philips Research Laboratories, Eindhoven, The Netherlands
Mohamed Azimane , Philips Research Laboratories, Eindhoven, The Netherlands
pp. 123

March iC-: An Improved Version of March C- for ADOFs Detection (Abstract)

P. Girard , Universit? de Montpellier II / CNRS, France
S. Pravossoudovitch , Universit? de Montpellier II / CNRS, France
A. Virazel , Universit? de Montpellier II / CNRS, France
L. Dilillo , Universit? de Montpellier II / CNRS, France
S. Borri , Infineon Technologies France
pp. 129
3C: Innovative Practices Session - Test Compression
4A: Paper Session - MEMs Testing and FPGA Testing

Multi-Modal Built-In Self-Test for Symmetric Microsystems (Abstract)

Nilmoni Deb , Carnegie Mellon University, Pittsburgh, PA
R. D. (Shawn) Blanton , Carnegie Mellon University, Pittsburgh, PA
pp. 139

A Dual-Mode Built-In Self-Test Technique for Capacitive MEMS Devices (Abstract)

Yu-Liang Wu , The Chinese University of Hong Kong, Shattin
Xingguo Xiong , University of Cincinnati, OH
Wen-Ben Jone , University of Cincinnati, OH
pp. 148

A Multi-Configuration Strategy for an Application Dependent Testing of FPGAs (Abstract)

Michel Renovell , LIRMM, France
Edward J. McCluskey , Stanford University, CA
Mehdi B. Tahoori , Northeastern University, Boston, MA
Philippe Faure , LIRMM, France
pp. 154
4B: Embedded Tutorial Session - Challenges in Embedded Memory Test and Diagnosis

null (PDF)

pp. null
4C: Innovative Practices Session - ITRS Key Challenge: High Speed I/Os

null (PDF)

pp. null
5A: Embedded Tutorial Session - Advances in Wafer Probe Test

null (PDF)

pp. null
5B: HotTopic Session - Testing of Nanocircuits with High Defect Densities

null (PDF)

pp. null
6A: Paper Session - Low-Voltage and Thermal Testing

The Pros and Cons of Very-Low-Voltage Testing: An Analysis based on Resistive Bridging Faults (Abstract)

Piet Engelke , Albert-Ludwigs-University, Germany
Bharath Seshadri , Purdue University, W. Lafayette, IN
Bernd Becker , Albert-Ludwigs-University, Germany
Michel Renovell , LIRMM - UMII, France
Ilia Polian , Albert-Ludwigs-University, Germany
pp. 171

Sensing temperature in CMOS circuits for Thermal Testing (Abstract)

A. Salhi , Universit? Bordeaux I, Bordeaux, France
A. Rubio , Universitat Polit?cnica de Catalunya, Barcelona, Spain
J. L. G?lvez , Universitat Polit?cnica de Catalunya, Barcelona, Spain
S. Dilhaire , Universit? Bordeaux I, Bordeaux, France
A. Ivanov , The University of British Columbia. Vancouver. Canada
A. Syal , The University of British Columbia. Vancouver. Canada
J. Altet , Universitat Polit?cnica de Catalunya, Barcelona, Spain
pp. 179

Detection of Temperature Sensitive Defects Using ZTC (Abstract)

Robert Madge , LSI Logic, Gresham
Ethan Long , Portland State University, Oregon
Brady Benware , LSI Logic, Fort Collins
W. Robert Daasch , Portland State University, Oregon
pp. 185
6B: Paper Session - Logic Built-In Self-Test

Planar High Performance Ring Generators (Abstract)

Grzegorz Mrugalski , Mentor Graphics Corporation, Wilsonville, OR
Janusz Rajski , Mentor Graphics Corporation, Wilsonville, OR
Nilanjan Mukherjee , Mentor Graphics Corporation, Wilsonville, OR
Jerzy Tyszer , Poznan University of Technology, Poland
pp. 193

Logic BIST Using Constrained Scan Cells (Abstract)

Wu-Tung Cheng , Mentor Graphics Corp., OR
Thomas Rinderknecht , Mentor Graphics Corp., OR
Liyang Lai , University of Illinois at Urbana-Champaign
Janak H. Patel , University of Illinois at Urbana-Champaign
pp. 199

BIST Technique by Equally Spaced Test Vector Sequences (Abstract)

E. Lupon , Universitat Polit?cnica de Catalunya, Spain
S. Manich , Universitat Polit?cnica de Catalunya, Spain
L. Balado , Universitat Polit?cnica de Catalunya, Spain
R. Rodr?guez , Universitat Polit?cnica de Catalunya, Spain
J. Figueras , Universitat Polit?cnica de Catalunya, Spain
L. Garc? , Universitat Polit?cnica de Catalunya, Spain
J. Rius , Universitat Polit?cnica de Catalunya, Spain
pp. 206
6C: Innovative Practices Session - Latest Results in WirelessTest
7A: Paper Session - Analog Testing I

Wafer-level RF Test and DfT for VCO Modulating Transceiver Architecures (Abstract)

Christian Olgaard , LitePoint Corp., San Jose, CA
Sule Ozev , Duke University, Durham, NC
pp. 217

GHz RF Front-end Bandwidth Time Domain Measurement (Abstract)

Mani Soma , University of Washington, Seattle
Yi Tang , University of Washington, Seattle
Qi Wang , University of Washington, Seattle
pp. 223

System-level Testing of RF Transmitter Specifications Using Optimized Periodic Bitstreams (Abstract)

Soumendu Bhattacharya , Georgia Institute of Technology, Atlanta
Sasikumar Cherubal , Texas Instruments, Dallas, TX
Abhijit Chatterjee , Georgia Institute of Technology, Atlanta
Achintya Halder , Georgia Institute of Technology, Atlanta
Ganesh Srinivasan , Georgia Institute of Technology, Atlanta
pp. 229
7B: Paper Session - Memory Testing II

Reducing Embedded SRAM Test Time under Redundancy Constraints (Abstract)

Josh Yang , University of British Columbia, Vancouver, Canada
Andr? Ivanov , University of British Columbia, Vancouver, Canada
Baosheng Wang , University of British Columbia, Vancouver, Canada
James Cicalo , University of British Columbia, Vancouver, Canada
Yervant Zorian , Virage Logic Corporation
pp. 237

Memory BIST Using ESP (Abstract)

Wu-Tung Cheng , Mentor Graphics Corporation, Wilsonville, Oregon
Joseph Rayhawk , Mentor Graphics Corporation, Wilsonville, Oregon
Don E. Ross , Mentor Graphics Corporation, Wilsonville, Oregon
Sudhakar M. Reddy , University of Iowa, Iowa City
Xiaogang Du , University of Iowa, Iowa City
pp. 243

A Methodology for Design and Evaluation of Redundancy Allocation Algorithms (Abstract)

S. Shoukourian , Virage Logic, Fremont, CA
V. A. Vardanian , Virage Logic, Fremont, CA
Y. Zorian , Virage Logic, Fremont, CA
pp. 249
7C: Innovative Practices Session - SoC Test Practice in Japan
8A: Paper Session - Analog Testing II

An On-Chip Transfer Function Characterization System for Analog Built-in Testing (Abstract)

Edgar S?nchez-Sinencio , Texas A&M University, College Station, TX
Jose Silva-Martinez , Texas A&M University, College Station, TX
Alberto Valdes-Garcia , Texas A&M University, College Station, TX
pp. 261

A Scalable On-Chip Jitter Extraction Technique (Abstract)

Dongwoo Hong , University of California, Santa Barbara
Li-C Wang , University of California, Santa Barbara
Kwang-Ting (Tim) Cheng , University of California, Santa Barbara
Chee-Kian Ong , University of California, Santa Barbara
pp. 267

Feature Extraction Based Built-In Alternate Test of RF Components Using a Noise Reference (Abstract)

Selim Sermet Akbay , Georgia Institute of Technology, Atlanta
Abhijit Chatterjee , Georgia Institute of Technology, Atlanta
pp. 273
8B: New Topic Session - Advances in 3D Packaging

null (PDF)

pp. null
8C: Innovative Practices Session - Challenges
9A: Embedded Tutorial Session - Reliability & Dependability

null (PDF)

pp. null
9B: Panel Session - Elevator Talks

null (PDF)

pp. null
9C: Panel Session - Process Variation - How Severe Is the Problem of Design & Test

null (PDF)

pp. null
10A: Paper Session - Defect Analysis and Fault Simulation

Defects and Faults in Quantum Cellular Automata at Nano Scale (Abstract)

Mehdi Baradaran Tahoori , Northeastern University, Boston, MA
Jing Huang , Northeastern University, Boston, MA
Fabrizio Lombardi , Northeastern University, Boston, MA
Mariam Momenzadeh , Northeastern University, Boston, MA
pp. 291

Generalized Sensitization using Fault Tuples (Abstract)

Kumar N. Dwarakanath , Carnegie Mellon University, Pittsburgh, PA
Sounil Biswas , Carnegie Mellon University, Pittsburgh, PA
R. D. (Shawn) Blanton , Carnegie Mellon University, Pittsburgh, PA
pp. 297

Fault Simulation Model for i{DDT} Testing: An Investigation (Abstract)

Jim Plusquellic , University of Maryland, Baltimore County
Abhishek Singh , University of Maryland, Baltimore County
Chintan Patel , University of Maryland, Baltimore County
pp. 304
10B: Paper Session - Issues in Reliability

A Diversified Memory Built-In Self-Repair Approach for Nanotechnologies (Abstract)

Lorena Anghel , TIMA Laboratory, Grenoble, France
Nadir Achouri , iRoC Technologies, Grenoble, France
Michael Nicolaidis , iRoC Technologies, Grenoble, France
pp. 313

Cost-Driven Selection of Parity Trees (Abstract)

Petros Drineas , Rensselaer Polytechnic Institute, Troy, NY
Sobeeh Almukhaizim , Yale University, New Haven, CT
Yiorgos Makris , Yale University, New Haven, CT
pp. 319

Soft Delay Error Effects in CMOS Combinational Circuits (Abstract)

Balkaran S. Gill , Case Western Reserve University, Cleveland, Ohio
Chris Papachristou , Case Western Reserve University, Cleveland, Ohio
Francis G. Wolff , Case Western Reserve University, Cleveland, Ohio
pp. 325
11A: Paper Session - Wireless and System Testing

Testing Systems Wirelessly (Abstract)

Arvinderpal Wander , University of Michigan, Ann Arbor
Nils Gura , Sun Microsystems Laboratories
Hans Eberle , Sun Microsystems Laboratories
pp. 335

Design of Wireless Sub-Micron Characterization System (Abstract)

Brian Moore , BigBangWidth, Inc.
Martin Margala , University of Rochester, New York
Chris Backhouse , University of Alberta, Edmonton, Canada
pp. 341

Boundary Scan for 5-GHz RF Pins Using LC Isolation Networks (Abstract)

Pei-Si Wu , National Taiwan University, Taipei
Jeng-Han Tsai , National Taiwan University, Taipei
Ren-Chieh Liu , National Taiwan University, Taipei
Tzi-Dar Chiueh , National Taiwan University, Taipei
Huei Wang , National Taiwan University, Taipei
Tian-Wei Huang , National Taiwan University, Taipei
pp. 347
11B: Paper Session - System-on-Chip Testing

Hybrid BIST for System-on-a-Chip Using an Embedded FPGA Core (Abstract)

Hideo Ito , Chiba University, Japan
Gang Zeng , Chiba University, Japan
pp. 355

Defect-Aware SOC Test Scheduling (Abstract)

Erik Larsson , Link?pings Universitet, Sweden
Julien Pouget , Montpellier 2 University, France
Zebo Peng , Link?pings Universitet, Sweden
pp. 361

Designing Reconfigurable Multiple Scan Chains for Systems-on-Chip (Abstract)

Saffat Quasem , University of Southern California
Sandeep Gupta , University of Southern California
pp. 367
11C: Innovative Practices Session - The Impact of SER

null (PDF)

pp. null
12A: Paper Session - Analog Testing and Design Validation

Prediction of Analog Performance Parameters Using Oscillation Based Test (Abstract)

Abhijit Chatterjee , Georgia Institute of Technology
Jacob A. Abraham , The University of Texas at Austin
Ashwin Raghunathan , The University of Texas at Austin
Hong Joong Shin , The University of Texas at Austin
pp. 377

An Approach to the Built-In Self-Test of Field Programmable Analog Arrays (Abstract)

M. Lubaszewski , Universidade Federal do Rio Grande do Sul, Porto Alegre, Brazil; Universidad de Sevilla, Spain
F. Aza? , Universit? de Montpellier II, France
T. Balen , Universidade Federal do Rio Grande do Sul, Porto Alegre, Brazil
M. Renovell , Universit? de Montpellier II, France
A. Andrade Jr. , Universidade Federal do Rio Grande do Sul, Porto Alegre, Brazil
pp. 383

Efficient ATPG for Design Validation Based On Partitioned State Exploration Histories (PDF)

Michael S. Hsiao , Virginia Tech, Blacksburg, VA
Qingwei Wu , Virginia Tech, Blacksburg, VA
pp. 389
12B: Embedded Tutorial Session - Design for Yield

null (PDF)

pp. null
12C: Innovative Practices Session - Optimizing Manufacturing Process
13A: Embedded Tutorial Session - Design for Manufacturability

null (PDF)

pp. null
13B: Hot Topic Session - Software-based Embedded Test

null (PDF)

pp. null
13C: Panel Session - Defect-based Testing and Burn-in: A Test Solution for Scaled Technology?

null (PDF)

pp. null

Author Index (PDF)

pp. 406
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