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2013 IEEE 31st VLSI Test Symposium (VTS) (2004)
Napa Valley, California
Apr. 25, 2004 to Apr. 29, 2004
ISSN: 1093-0167
ISBN: 0-7695-2134-7
pp: 199
Wu-Tung Cheng , Mentor Graphics Corp., OR
Thomas Rinderknecht , Mentor Graphics Corp., OR
Liyang Lai , University of Illinois at Urbana-Champaign
Janak H. Patel , University of Illinois at Urbana-Champaign
This paper presents a novel scan cell based control point insertion technique which eliminates timing degradation of conventional control points in built-in self test (BIST) applications. In this approach, control points are encoded into scan chains. Observation points are applied to enhance fault coverage. At each phase, a set of control points are activated to detect a set of target faults. Compared to conventional test point insertion, scan cell based control points improve controllability of the core logic without compromising timing performance of circuit under test (CUT). Experimental results show that close to stuck-at fault coverage by automatic test pattern generation (ATPG) can be achieved by our BIST method.
Wu-Tung Cheng, Thomas Rinderknecht, Liyang Lai, Janak H. Patel, "Logic BIST Using Constrained Scan Cells", 2013 IEEE 31st VLSI Test Symposium (VTS), vol. 00, no. , pp. 199, 2004, doi:10.1109/VTEST.2004.1299244
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