The Community for Technology Leaders
2013 IEEE 31st VLSI Test Symposium (VTS) (2003)
Napa Valley, California
Apr. 27, 2003 to May 1, 2003
ISSN: 1093-0167
ISBN: 0-7695-1924-5
TABLE OF CONTENTS

Foreword (PDF)

pp. xiv

Program Committee (PDF)

pp. xviii

Reviewers (PDF)

pp. xix
Plenary Session

Welcome Address (PDF)

pp. null
Session 1A: New Directions in Scan Test

null (PDF)

pp. null

A Reconfigurable Shared Scan-in Architecture (Abstract)

Samitha Samaranayake , Massachusetts Institute of Technology
Nodari Sitchinava , Massachusetts Institute of Technology
Rohit Kapur , Synopsys Inc.
Emil Gizdarski , Synopsys Inc.
Frederic Neuveux , Synopsys Inc.
T. W. Williams , Synopsys Inc.
pp. 9

Test Data Compression and Test Time Reduction of Longest-Path-Per-Gate Tests based on Illinois Scan Architecture (Abstract)

Janak H. Patel , University of Illinois at Urbana Champaign
Manish Sharma , University of Illinois at Urbana Champaign
Jeff Rearick , Agilent Technologies
pp. 15
Session 1B: Outlier Identification & Current Based Test

null (PDF)

pp. null

Use of Multiple IDDQ Test Metrics for Outlier Identification (Abstract)

D. M. H. Walker , Texas A&M University
Sagar S. Sabade , Texas A&M University
pp. 31

Effectiveness Comparisons of Outlier Screening Methods for Frequency Dependent Defects on Complex ASICs (Abstract)

R. Daasch , Portland State University
C. Lu , LSI Logic Corporation
B. R. Benware , LSI Logic Corporation
R. Madge , LSI Logic Corporation
pp. 39
IP Session 1C: How to Get to Open Architecture ATE?

null (PDF)

pp. null
Session 2A: Advances in Built-In Self-Test - I

null (PDF)

pp. null

High Speed Ring Generators and Compactors of Test Data (Abstract)

Janusz Rajski , Mentor Graphics Corporation
Grzegorz Mrugalski , Poznan University of Technology
Jerzy Tyszer , Poznan University of Technology
pp. 57

BUILT-IN RESEEDING FOR SERIAL BIST (Abstract)

Ahmad A. Al-Yamani , Stanford University
Edward J. McCluskey , Stanford University
pp. 63

BIST RESEEDING WITH VERY FEW SEEDS (Abstract)

Edward J. McCluskey , Stanford University
Ahmad A. Al-Yamani , Stanford University
Subhasish Mitra , Intel Corporation
pp. 69
Session 2B: Analog and Mixed-Signal Test - I

null (PDF)

pp. null

Ultra Low Cost Analog BIST Using Spectral Analysis (Abstract)

Luigi Carro , Universidade Federal do Rio Grande do Sul - UFRGS
Marcelo Negreiros , Universidade Federal do Rio Grande do Sul - UFRGS
Altamiro Amadeu Susin , Universidade Federal do Rio Grande do Sul - UFRGS
pp. 77

DSP-Based Statistical Self Test of On-Chip Converters (Abstract)

Hak-soo Yu , The University of Texas at Austin
Jacob A. Abraham , The University of Texas at Austin
Sungbae Hwang , The University of Texas at Austin
pp. 83
IP Session 2C: Silicon Proven IP Cores

null (PDF)

pp. null
Session 3A: Test Compaction

null (PDF)

pp. null

Analysis and Design of Optimal Combinational Compactors (Abstract)

Leendert Huisman , IBM Microelectronics
Peter Wohl , Synopsys Inc.
pp. 101

Application of Saluja-Karpovsky Compactors to Test Responses with Many Unknowns (Abstract)

Steven S. Lumetta , University of Illinois
Sudhakar M. Reddy , University of Iowa
Janak H. Patel , University of Illinois
pp. 107
Session 3B: Testing Buses and On-Chip Interconnect

null (PDF)

pp. null

Eliminating Non-Determinism During Test of High-Speed Source Synchronous Differential Buses (Abstract)

Nur A. Touba , University of Texas at Austin
Kartik Mohanram , University of Texas at Austin
pp. 121

The Impact of NoC Reuse on the Testing of Core-based Systems (Abstract)

M. Lubaszewski , PPGC - Inst. de Inform?tica; PPGEE - Depto. Engenharia El?trica
C.A. Zeferino , PPGC - Inst. de Inform?tica; Centro de Ci?ncias Tecnol?gicas da Terra e do Mar - Univali
L. Carro , PPGC - Inst. de Inform?tica; PPGEE - Depto. Engenharia El?trica
M. Kreutz , PPGC - Inst. de Inform?tica
A. Susin , PPGC - Inst. de Inform?tica; PPGEE - Depto. Engenharia El?trica
E. Cota , PPGC - Inst. de Inform?tica
pp. 128
IP Session 3C: Test and Diagnosis of ICs Using 130 nm & 90 nm Technologies

null (PDF)

pp. null
Session 4A: Test Challenges in Nanometer Technologies

null (PDF)

pp. null

Threshold Voltage Mismatch (\DeltaV<sub>T</sub>) Fault Modeling (Abstract)

Jos? Pineda de Gyvez , Philips Research Laboratories
Rosa Rodr?guez-Monta? , Philips Research Laboratories
pp. 145

Test Generation for Maximizing Ground Bounce Considering Circuit Delay (Abstract)

Yi-Shing Chang , Intel Corp
Melvin A. Breuer , University of Southern California
Sandeep K. Gupta , University of Southern California
pp. 151

Testing SoC Interconnects for Signal Integrity Using Boundary Scan (Abstract)

M. Nourani , The University of Texas at Dallas
N. Ahmed , The University of Texas at Dallas
M. H. Tehranipour , The University of Texas at Dallas
pp. 158
IP Session 4C: Test Data Analysis

null (PDF)

pp. null
Special Session 5A: Panel
Special Session 5B: Panel
Session 6A: Advanced Test Generation and Fault Simulation Techniques

null (PDF)

pp. null

An Efficient Test Relaxation Technique for Synchronous Sequential Circuits (Abstract)

Aiman El-Maleh , King Fahd University of Petroleum and Minerals
Khaled Al-Utaibi , King Fahd University of Petroleum and Minerals
pp. 179

Path-Delay Fault Simulation for Circuits with Large Numbers of Paths for Very Large Test Sets (Abstract)

Nabil M. Abdulrazzaq , United Arab Emirates University
Sandeep K. Gupta , University of Southern California
pp. 186
Session 6B: Analog and Mixed-Signal Test - 2

null (PDF)

pp. null

1149.4 Based On-Line Quiescent State Monitoring Technique (Abstract)

IS Tseng , Chroma ATE Inc.
Chih-Hu Wang , National Central Univ.
Wei-Juo Wang , National Central Univ.
Chauchin Su , National Chiao Tung University
pp. 197

Measurement of Phase and Frequency Variations in Radio-Frequency Signals (Abstract)

Welela Haileselassie , University of Washington, Seattle
Jessica Sherrid , University of Washington, Seattle
Mani Soma , University of Washington, Seattle
pp. 203
IP Session 6C: Testing High Speed I/Os

null (PDF)

pp. null
Session 7A: Test Data Compression

null (PDF)

pp. null

Efficient Seed Utilization for Reseeding based Compression (Abstract)

Erik H. Volkerink , Stanford University; Agilent Laboratories
Subhasish Mitra , Intel Corporation
pp. 232
Session 7B: Memory Testing

null (PDF)

pp. null

Detecting Intra-Word Faults in Word-Oriented Memories (Abstract)

Ad J. van de Goor , Delft University of Technology
Said Hamdioui , Intel Corporation; Delft University of Technology
Mike Rodgers , Intel Corporation
pp. 241

Test and Diagnosis of Word-Oriented Multiport Memories (Abstract)

Chih-Tsun Huang , National Tsing Hua University
Cheng-Wen Wu , National Tsing Hua University
Kuo-Liang Cheng , National Tsing Hua University
Chih-Wea Wang , National Tsing Hua University
pp. 248

Generating Complete and Optimal March Tests for Linked Faults in Memories (Abstract)

Sultan M. Al-Harbi , Kuwait University
Sandeep K. Gupta , University of Southern California
pp. 254
IP Session 7C: ATE Facilities for Modular SoC Testing

null (PDF)

pp. null
Session 8A: Power Consumption and Test

null (PDF)

pp. null

Power Constrained Test Scheduling with Dynamically Varied TAM (Abstract)

Shambhu Upadhyaya , State University of New York at Buffalo
Dan Zhao , State University of New York at Buffalo
pp. 273

Development of Energy Consumption Ratio Test (Abstract)

Xiaoyun Sun , University of Minnesota
Bapiraju Vinnakota , University of Minnesota
Larry Kinney , University of Minnesota
pp. 279
Session 8B: Testing Core-Based SoCs

null (PDF)

pp. null

Design for Consecutive Transparency of Cores in System-on-a-Chip (Abstract)

Tomokazu Yoneda , Nara Institute of Science and Technology
Hideo Fujiwara , Nara Institute of Science and Technology
pp. 287

An Embedded Autonomous Scan-Based Results Analyzer (EARA) for SoC Cores (Abstract)

Andr? Ivanov , University of British Columbia
Mohsen Nahvi , University of British Columbia
pp. 293
IP Session 8C: Layout Driven Design for Test & Manufacturability

null (PDF)

pp. null
Special Session 9A: Panel
Special Session 9B: Panel
Special Session 9C: Panel

Embedded Tutorial: Test Consideration for Nanometer Scale CMOS Circuits (Abstract)

Kwang-Ting Cheng , Univ. of California-Santa Barbara
Kaushik Roy , Purdue University
T.M. Mak , Intel Corp
pp. 313
Session 10A: System-Level Test Issues

null (PDF)

pp. null

Test Resource Partitioning and Optimization for SOC Designs (Abstract)

Erik Larsson , Linkopings Universitet; Nara Institute of Science and Technology
Hideo Fujiwara , Nara Institute of Science and Technology
pp. 319

SOC Test Scheduling Using Simulated Annealing (Abstract)

Wei Zou , University of Iowa
Sudhakar M. Reddy , University of Iowa
Yu Huang , Mentor Graphics Corporation
Irith Pomeranz , Purdue University
pp. 325

Layered Approach to Designing System Test Interfaces (Abstract)

Zeljko Zilic , McGill University
Man Wah Chiang , McGill University
pp. 331
Session 10B: Diagnosis Techniques

null (PDF)

pp. null

Diagnosis of Delay Defects Using Statistical Timing Models (Abstract)

Angela Krstic , University of California, Santa Barbara
Li-C. Wang , University of California, Santa Barbara
Jing-Jia Liou , National Tsing-Hua University, Taiwan
Kwang-Ting Cheng , University of California, Santa Barbara
pp. 339

Improving Diagnostic Resolution of Delay Faults using Path Delay Fault Model (Abstract)

Maurice Lousberg , Philips Research Laboratories
Guido Gronthoud , Philips Research Laboratories
Ananta K. Majhi , Philips Research Laboratories
Camelia Hora , Philips Research Laboratories
Stefan Eichenberger , Philips Semiconductors
Pop Valer , Univ. of Twente
pp. 345
Session 11A: Advances in Built-In Self-Test - 2

null (PDF)

pp. null

BIST-Aided Scan Test - A New Method for Test Cost Reduction (Abstract)

Hideaki Konishi , Fujitsu Ltd.
Koichi Itaya , Fujitsu Ltd.
Hitoshi Yamanaka , Fujitsu Ltd.
Takashi Mochiyama , Fujitsu Ltd.
Kwame Osei Boateng , Fujitsu Laboratories Ltd.
Michiaki Emori , Fujitsu Ltd.
Takahisa Hiraide , Fujitsu Laboratories Ltd.
pp. 359

Built-In TPG with Designed Phaseshifts (Abstract)

Dimitri Kagaris , Southern Illinois University
pp. 365

A Test Interface for Built-In Test of Non-Isolated Scanned Cores (Abstract)

Irith Pomeranz , Purdue University
Sudhakar M. Reddy , University of Iowa
Yervant Zorian , Logic Vision
pp. 371
Session 11B: Test in the Presence of Bridging Faults

null (PDF)

pp. null

A Circuit Level Fault Model for Resistive Opens and Bridges (Abstract)

Weiping Shi , Texas A&M University
D. M. H. Walker , Texas A&M University
Wangqi Qiu , Texas A&M University
Xiang Lu , Texas A&M University
Zhuo Li , Texas A&M University
pp. 379

Analyzing Crosstalk in the Presence of Weak Bridge Defects (Abstract)

Melvin A. Breuer , University of Southern California
Shahin Nazarian , University of Southern California
Shahdad Irajpour , University of Southern California
Sandeep K. Gupta , University of Southern California
Lei Wang , University of Southern California
pp. 385

Efficient Implication - Based Untestable Bridge Fault Identifier (PDF)

Michael S. Hsiao , Virginia Tech
Manan Syal , Virginia Tech
Sreejit Chakravarty , Intel Corporation
Kiran B. Doreswamy , Intel Corporation
pp. 393
IP Session 11C: SoC Test Practices for Consumer Products

null (PDF)

pp. null
Session 12A: Emerging Circuit Technologies: Test Challenges

null (PDF)

pp. null

Testable Design and Testing of Micro-Electro-Fluidic Arrays (Abstract)

Mustafa Acar , MESA+ Research Institute
Hans G. Kerkhoff , MESA+ Research Institute
pp. 403

Fault Testing for Reversible Circuits (Abstract)

Igor L. Markov , University of Michigan
John P. Hayes , University of Michigan
Ketan N. Patel , University of Michigan
pp. 410

Design for Self-Checking and Self-Timed Datapath (Abstract)

Cheong-fat Chan , The Chinese University of Hong Kong
Chiu-sing Choy , The Chinese University of Hong Kong
Kong-pong Pun , The Chinese University of Hong Kong
Jing-ling Yang , The University of Hong Kong
pp. 417
IP Session 12C: P1500 DFT Disclosure Document: A Standard to Communicate Mergeable Core DFT Data

null (PDF)

pp. null

Using DFT Disclosure Information for Economic Merging of Soft Cores (PDF)

S. Bhawmik , University of Siegen, Agere
M. Wahl , University of Siegen, Agere
pp. null
Special Session 13A: Panel
Special Session 13B: Panel
Special Session 13C: Panel

Author's Index (PDF)

pp. 431
99 ms
(Ver 3.1 (10032016))