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2013 IEEE 31st VLSI Test Symposium (VTS) (2002)
Monterey, California
Apr. 28, 2002 to May 2, 2002
ISBN: 0-7695-1570-3
TABLE OF CONTENTS

Foreword (PDF)

pp. xvi

Acknowledgements (PDF)

pp. xviii

Program Committee (PDF)

pp. xxiii

Reviewers (PDF)

pp. xxiv
Welcome Message: Joan Figueras, General Chair

Keynote Address (PDF)

Michael Hackworth , Cirrus Logic, Inc.
pp. xxxv
Program Introduction: Andre Ivanov, Program Chair
Session 1: Microprocessor Test: Moderators: M. d'Abreau, Ample Communications

Novel Techniques for Achieving High At-Speed Transition Fault Test Coverage for Motorola's Microprocessors Based on PowerPC(tm) Instruction Set Architecture (Abstract)

Xijiang Lin , Mentor Graphics Corporation
Bruce Swanson , Mentor Graphics Corporation
Nandu Tendolkar , Motorola, Inc.
Rick Woltenberg , Motorola, Inc.
Greg Aldrich , Mentor Graphics Corporation
Rajesh Raina , Motorola, Inc.
pp. 0003

Reconfiguration Technique for Reducing Test Time and Test Data Volume in Illinois Scan Architecture Based Designs (Abstract)

Amit R. Pandey , University of Illinois at Urbana-Champaign
Tanak H. Patel , University of Illinois at Urbana-Champaign
pp. 0009
Session 2: Applications of Very Low Voltage and Slow Speed Testing: Moderators: K. Eshraghian, Edith Cowan University

Very Low Voltage Testing of SOI Integrated Circuits (Abstract)

Eric MacDonald , IBM Microelectronics Division
Nur A. Touba , University of Texas at Austin
pp. 0025

Performance Comparison of VLV, ULV, and ECR Tests (Abstract)

Wanli Jiang , Guidant Corporation
Eric Peterson , Guidant Corporation
pp. 0031

Experimental Results for Slow-Speed Testing (Abstract)

Edward J. McCluskey , Stanford University
Chao-Wen Tseng , Stanford University
James Li , Stanford University
pp. 0037
IP Session 1: Innovations in Test Automation

Innovations in Test Automation (PDF)

Janusz Rajski , Mentor Graphics Corp.
Michael Howells , Logic Vision Inc.
Jim Sproch , Synopsys Inc.
pp. 0043
Session 3: Advancements in Scan-Based Testing: Moderators: M. Lousberg, Philips

Scan-Path with Directly Duplicated and Inverted Duplicated Registers (Abstract)

M. Goessel , University of Potsdam
A. Singh , Auburn University
E. Sogomonyan , University of Potsdam
pp. 0047

An Efficient Test Relaxation Technique for Combinational & Full-Scan Sequential Circuits (Abstract)

Aiman El-Maleh , King Fahd University of Petroleum and Minerals
Ali Al-Suwaiyan , King Fahd University of Petroleum and Minerals
pp. 0053
Session 4: Burn-in Reduction or Alternatives: Moderators: K. Mandl, Teradyne

Yield-Reliability Modeling: Experimental Verification and Application to Burn-In Reduction (Abstract)

Adit D. Singh , Auburn University
Kathleen Purdy , IBM Microelectronics
Thomas S. Barnett , Auburn University
Matt Grady , IBM Microelectronics
pp. 0075
IP Session 2: DFT Testers 1
Session 5: Test Set Compression Techniques: Moderators: K. Butler, Texas Instruments

How Effective are Compression Codes for Reducing Test Data Volume? (Abstract)

Krishnendu Chakrabarty , Duke University
Anshuman Chandra , Duke University
Rafael A. Medina , Massachusetts Institute of Technology
pp. 0091

Test Vector Compression Using EDA-ATE Synergies (Abstract)

Erik Volkerink , Agilent Technologies, Inc.
Ajay Khoche , Agilent Technologies, Inc.
Jochen Rivoir , Agilent Technologies, Inc.
Subhasish Mitra , Intel Corporation
pp. 0097

On Test Data Volume Reduction for Multiple Scan Chain Designs (Abstract)

Kohei Miyase , Kyushu Institute of Technology
Sudhakar M. Reddy , University of Iowa
Seiji Kajihara , Kyushu Institute of Technology
Irith Pomeranz , Purdue University
pp. 0103
Session 6: Analog BIST: Moderators: J. da Franca, ChipIdea

Spectrum-Based BIST in Complex SOCs (PDF)

Michael S. Hsiao , Virginia Tech
Ganapathy Kasturirangan , Intel Corporation
pp. 0111

A Self Calibrated ADC BIST Methodology (Abstract)

Hung-kai Chen , Nation Central University
Chau-chin Su , Nation Central University
Chih-hu Wang , Nation Central University
pp. 0117

Self-Testing Second-Order Delta-Sigma Modulators Using Digital Stimulus (Abstract)

Chee-Kian Ong , University of California at Santa Barbara
Kwang-Ting (Tim) Cheng , University of California at Santa Barbara
pp. 0123
IP Session 3: DFT Testers 2
Session 7: Increased Efficiency Testing: Moderators: B. Pouya, Banderacom

Testing High-Speed SoCs Using Low-Speed ATEs (Abstract)

James Chin , Texas Instruments,Inc.
Mehrdad Nourani , University of Texas at Dallas
pp. 0133

Software-Based Weighted Random Testing for IP Cores in Bus-Based Programmable SoCs (Abstract)

Madhu K. Iyer , University of California at Santa Barbara
Kwang-Ting Cheng , University of California at Santa Barbara
pp. 0139

On Using Efficient Test Sequences for BIST (Abstract)

P. Girard , Laboratoire d ?Informatique de Robotique et de Micro?lectronique de Montpellier
C. Landrault , Laboratoire d ?Informatique de Robotique et de Micro?lectronique de Montpellier
S. Pravossoudovitch , Laboratoire d ?Informatique de Robotique et de Micro?lectronique de Montpellier
A. Virazel , Laboratoire d ?Informatique de Robotique et de Micro?lectronique de Montpellier
R. David , Laboratoire d ?Automatique de Grenoble
pp. 0145
Session 8: Controlling and Reducing Test Power: Moderators: A. Crouch, Inovys

Controlling Peak Power During Scan Testing (Abstract)

Nur A. Touba , University of Texas at Austin
Ranganathan Sankaralingam , University of Texas at Austin
pp. 0153

Test Vector Modification for Power Reduction during Scan Testing (Abstract)

Kohei Miyase , Kyushu Institute of Technology
Koji Ishida , Kyushu Institute of Technology
Seiji Kajihara , Kyushu Institute of Technology
pp. 0160

Test Power Reduction through Minimization of Scan Chain Transitions (Abstract)

Alex Orailoglu , University of California at San Diego
Ismet Bayraktaroglu , University of California at San Diego
Ozgur Sinanoglu , University of California at San Diego
pp. 0166
IP Session 4

Wireless Test (PDF)

John McLaughlin , Agilent Technologies
Mustapha Slamani , IBM Microelectronics
William R. Eisenstadt , University of Florida
H. Ding , IBM Microelectronics
Sanghoon Choi , University of Florida
Robert Aitken , Agilent Technologies
pp. 0173
Special Session 1: Panel

Analog and Mixed Signal BIST: Too Much, Too Little, Too Late? (PDF)

William De Wilkins , National Semiconductor
Lee Song , Teradyne
Sassan Tabatabaei , Vector 12
Fidel Muradali , Agilent Technologies
Ken Posse , Teseda
Barry Baril , Credence
pp. 0175
Special Session 2: Panel

Test as a Key Enabler for Faster Yield Ramp-Up (PDF)

R. Aitke , Agilent Technologies
R. Seger , Philips
Rene Segers , Philips
Julie Segal , HPL Technology
M. Millegen , HPL Technology
S. Eichenberge , Philips
pp. 0177
Session 9: Diagnosis: Moderators: F. Maamari, LogicVision

Diagnosis of Sequence-Dependent Chips (Abstract)

E. J. McCluskey , Stanford University
James C.-M. Li , Stanford University
pp. 0187
Session 10: Analog Circuit Testing: Moderators: J. Abraham, University of Texas at Austin

Filters Designed for Testability Wrapped on the Mixed-Signal Test Bus (Abstract)

Vladimir Castro Alves , Federal University of Rio de Janeiro
Jose Vicente Calvano , Brazilian Navy Research Institute
Antonio C. Mesquita , Federal University of Rio de Janeiro
Marcelo Lubaszewski , Federal University of Rio Grande do Su
pp. 0201

Timing Jitter Measurement of 10 Gbps Bit Clock Signals Using Frequency Division (Abstract)

Louis Malarsie , Agere Systems
Hirobumi Musha , Advantest Corporation
Mani Soma , University of Washington
Masahiro Ishida , Advantest Laboratories, Ltd.
Takahiro J. Yamaguchi , Advantest Laboratories, Ltd.
pp. 0207

Boosting the Accuracy of Analog Test Coverage Computation through Statistical Tolerance Analysis (Abstract)

Alex Orailoglu , University of California at San Diego
Sule Ozev , University of California at San Diego
pp. 0213
Session 11: High Level Test Techniques: Moderators: J. Aylor, Virginia Tech

Instruction-Based Self-Testing of Processor Cores (Abstract)

N. Kranitis , University of Athens
Y. Zorian , LogicVision
D. Gizopoulos , University of Piraeus
A. Paschalis , University of Athens
pp. 0223

An Industrial Environment for High-Level Fault-Tolerant Structures Insertion and Validation (Abstract)

Luis Berrojo , Alcatel Espacio, S.A.
Fulvio Corno , Politecnico di Torino
Luis Entrena , Universitad Carlos III
Matteo Sonza-Reorda , Politecnico di Torino
Isabel González , Alcatel Espacio, S.A.
Celia Lopez , Universitad Carlos III
Giovanni Squillero , Politecnico di Torino
pp. 0229

Program Slicing for Hierarchical Test Generation (Abstract)

Vivekananda M. Vedula , University of Texas at Austin
Jacob A. Abraham , University of Texas at Austin
Jayanta Bhadra , Motorola Inc.
pp. 0237
Session 12: SoC Test Infrastructure: Moderators: M. Mowji, LogicVision

Design for Testability and Testing of IEEE 1149.1 Tap Controller (Abstract)

Samy Makar , Transmeta Corporation
Subhasish Mitra , Intel Corporation
Edward J. McCluskey , Stanford University
pp. 0247

On Using Rectangle Packing for SOC Wrapper/TAM Co-Optimization (Abstract)

Vikram Iyengar , Duke University
Krishnendu Chakrabarty , Duke University
Erik Jan Marinissen , Philips Research Laboratories
pp. 0253

Cluster-Based Test Architecture Design for System-on-Chip (Abstract)

Erik Jan Marinissen , Philips Research Laboratories
Sandeep Kumar Goel , Philips Research Laboratories
pp. 0259
IP Session 5: Multi-GigaHertz Testing Challenges and Solutions

Multi-GigaHertz Testing Challenges and Solutions (PDF)

Klaus-Dieter Hilliges , Agilent Technologies
Sassan Tabatabaei , Vector 12
Karim Arabi , PMC Sierra
David Keezer , Georgia Institute of Technology
pp. 0265
Session 13: Test Tools and Algorithms: Moderators: T. Williams, Synopsys

Exploiting Dominance and Equivalence using Fault Tuples (Abstract)

R. D. (Shawn) Blanton , Carnegie Mellon University
Kumar N. Dwarakanat , Carnegie Mellon University
pp. 0269

RAMSES-FT: A Fault Simulator for Flash Memory Testing and Diagnostics (Abstract)

Kuo-Liang Cheng , National Tsing Hua University
Chih-Tsun Huang , National Tsing Hua University
Cheng-Wen Wu , National Tsing Hua University
Jen-Chieh Yeh , National Tsing Hua University
Chih-Wea Wang , National Tsing Hua University
pp. 0281
Session 14: Supply Current Testing: Moderators: T. Storey, PDF

Speeding-Up IDDQ Measurements (Abstract)

C. Thibeault , ?cole de Technologie Sup?rieure
pp. 0295
Special Session 3: Panel

Debating the Future of Burn-In (PDF)

Bob Madge , LSI Logic
Phil Nigh , IBM
Mike Rodgers , Intel Corporation
Edward J. McCluske , Stanford University
Subhasish Mitra , Agilent Technologies
Peter Maxwell , Agilent Technologies
pp. 0311
Special Session 4: Hot Topic

Beyond CMOS (PDF)

M. Forshaw , University College, London
B. Courtoi , TIMA
pp. 0315
Special Session 5: Embedded Tutorial
Session 15: Test Pattern Generation: Moderators: J. Hayes, University of Michigan

A Method of Test Generation for Path Delay Faults in Balanced Sequential Circuits (Abstract)

Shunjiro Miwa , NEC Corporation
Satoshi Ohtake , Nara Institute of Science and Technology
Hideo Fujiwara , Nara Institute of Science and Technology
pp. 0321

A Test Generation Method Using a Compacted Test Table and a Test Generation Method Using a Compacted Test Plan Table for RTL Data Path Circuits (Abstract)

Toshinori Hosokawa , Semiconductor Technology Academic Research Center
Hiroshi Date , Semiconductor Technology Academic Research Center
Michiaki Muraoka , Semiconductor Technology Academic Research Center
pp. 0328

Test Pattern Generation for Signal Integrity Faults on Long Interconnects (Abstract)

Amir Attarha , LSI Logic, Corporation
Mehrdad Nourani , University of Texas at Dallas
pp. 0336
Session 16: Tester Hardware Modeling and Improvements: Moderators: M. Topsakal, Cypress

Improved Test Monitor Circuit in Power Pin DfT (Abstract)

Frans de Jong , Philips Research
Rodger Schuttert , Philips Research
Ben Kup , Philips Consumer Electronics
pp. 0345

Measuring Stray Capacitance on Tester Hardware (Abstract)

John Ridley , Texas Instruments Inc.
Achintya Halder , Georgia Institute of Technology
Abhijit Chatterjee , Georgia Institute of Technology
Pramod Variyam , Texas Instruments Inc.
pp. 0351

Power Supply Transient Signal Analysis Under Real Process and Test Hardware Models (Abstract)

Anne Gattiker , IBM Austin Research Labs
Jim Plusquellic , University of Maryland at Baltimore County
Abhishek Singh , University of Maryland at Baltimore County
pp. 0357
Session 17: Fault Modeling & Extraction: Moderators: G. Robinson, 3MTS

Layout Analysis to Extract Open Nets Caused by Systematic Failure Mechanisms (Abstract)

Kambiz Komeyli , Intel Corporation
Sujit T. Zachariah , Intel Corporation
Michael J. Carruthers , Intel Corporation
Bret T. Stastny , Intel Corporation
Sreejit Chakravarty , Intel Corporation
Eric W. Savage , Intel Corporation
pp. 0367

Fault Models for Speed Failures Caused by Bridges and Opens (Abstract)

Ankur Jain , Intel Corporation
Sreejit Chakravarty , Intel Corporation
pp. 0373

Timed Test Generation Crosstalk Switch Failures in Domino CMOS Circuits (Abstract)

Rahul Kundu , Carnegie Mellon University
R. D. (Shawn) Blanton , Carnegie Mellon University
pp. 0379
Session 18: Memory Testing: Moderators: N. Saxena, Chip Engines

Testing and Diagnosing Embedded Content Addressable Memories (Abstract)

Jin-Fu Li , National Tsing Hua University
Ruey-Shing Tzeng , National Tsing Hua University
Cheng-Wen Wu , National Tsing Hua University
pp. 0389

Testing Static and Dynamic Faults in Random Access Memories (Abstract)

Ad J. van de Goor , Delft University of Technology
Said Hamdioui , Intel Corporation and Delft University of Technology
Zaid Al-Ars , Delft University of Technology
pp. 0395

Approximating Infinite Dynamic Behavior for DRAM Cell Defects (Abstract)

Zaid Al-Ars , Delft University of Technology
Ad J. van de Goor , Delft University of Technology
pp. 0401
IP Session 8

Validation and Test of Network Processors and ASICs (PDF)

C.-H. Chia , Lucent
Haluk Konuk , Broadcom
Faraydon Karim , ST Microelectronics
Keesup Kim , Intel
Sujit Dey , University of California at San Diego
pp. 0407
Session 19: Test-Cost Reduction: Moderators: D. Edenfeld, Intel

Test Economics for Multi-site Test with Modern Cost Reduction Techniques (Abstract)

Klaus D. Hilliges , Agilent Laboratories
Jochen Rivoir , Agilent Laboratories
Ajay Khoche , Agilent Laboratories
Erik H. Volkerink , Agilent Laboratories
pp. 0411

LI-BIST: A Low-Cost Self-Test Scheme for SoC Logic Cores and Interconnects (Abstract)

Krishna Sekar , University of California at San Diego
Sujit Dey , University of California at San Diego
pp. 0417

Useless Memory Allocation in System-on-a-Chip Test: Problems and Solutions (Abstract)

Nicola Nicolici , McMaster University
Bashir M. Al-Hashimi , University of Southampton
Paul T. Gonciari , University of Southampton
pp. 0423
Session 20: Oscillation - Based Test: Moderators: B. Kaminska, IMS

Practical Solutions for the Application of the Oscillation-Based-Test: Start-Up and On-Chip Evaluation (Abstract)

Adoración Rueda , Universidad de Sevilla
Diego Vázquez , Universidad de Sevilla
Gloria Huertas , Universidad de Sevilla
José L. Huertas , Universidad de Sevilla
Gildas Leger , Universidad de Sevilla
pp. 0433

Evaluation of the Oscillation-based Test Methodology for Micro-Electro-Mechanical Systems (Abstract)

Y. Bertrand , Laboratoire d ?Informatique de Robotique et de Micro?lectronique de Montpellier
P. Nouet , Laboratoire d ?Informatique de Robotique et de Micro?lectronique de Montpellier
V. Beroulle , Laboratoire d ?Informatique de Robotique et de Micro?lectronique de Montpellier
L. Latorre , Laboratoire d ?Informatique de Robotique et de Micro?lectronique de Montpellier
pp. 0439
Special Session 6: Panel
Special Session 7: Embedded Tutorial

Challenges in Nanometric Technology Scaling: Trends and Projections (PDF)

Jaume Segura , University of Illes Balears
Vivek De , Intel Corporation
Ali Keshavarzi , Intel Corporation
pp. 0447
Special Session 8: Panel

SoCs with MEMS? Can We Include MEMS in the SoCs Design and Test Flow? (PDF)

R. D. Blanton , Carnegie-Mellon University
H. Kerkhoff , MESA Institute
H. Bederr , Motorola
S. Mir , IMAG
H. J. Klim , ETEC Inc.
pp. 0449

Author Index (PDF)

pp. 0451
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