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Proceedings 20th IEEE VLSI Test Symposium (VTS 2002) (2002)
Monterey, California
Apr. 28, 2002 to May 2, 2002
ISBN: 0-7695-1570-3
pp: 0009
Amit R. Pandey , University of Illinois at Urbana-Champaign
Tanak H. Patel , University of Illinois at Urbana-Champaign
ABSTRACT
As the complexity of VLSI circuits is increasing due to the exponential rise in transistor count per chip, testing cost is becoming an important factor in the overall integrated circuit (IC) manufacturing cost. This paper addresses the issue of decreasing test cost by lowering the test data bits and the number of clock cycles required to test a chip. We propose a technique based on the reconfiguration of scan chains to reduce test time and test data volume for Illinois Scan Architecture (ILS) based designs. This technique is presented with details of hardware implementation as well as the test generation and test application procedures. The reduction in test time and test data volume achieved using this technique is quite signi .cant in most circuits.
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CITATION

A. R. Pandey and T. H. Patel, "Reconfiguration Technique for Reducing Test Time and Test Data Volume in Illinois Scan Architecture Based Designs," Proceedings 20th IEEE VLSI Test Symposium (VTS 2002)(VTS), Monterey, California, 2002, pp. 0009.
doi:10.1109/VTS.2002.1011104
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