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2013 IEEE 31st VLSI Test Symposium (VTS) (2001)
Marina Del Rey, CA
Mar. 29, 2001 to Apr. 3, 2001
ISBN: 0-7695-1122-8
TABLE OF CONTENTS

Foreword (PDF)

pp. xiii

Acknowledgements (PDF)

pp. xiv

Program Committee (PDF)

pp. xviii

Reviewers (PDF)

pp. xix
Keynote Address
Invited Presentation
Session 1: BIST Techniques

Hybrid BIST Based on Weighted Pseudo-Random Testing: A New Test Resource Partitioning Scheme (Abstract)

Abhijit Jas , University of Texas, Austin
C.V. Krishna , University of Texas, Austin
Nur A. Touba , University of Texas, Austin
pp. 0002

Compression Technique for Interactive BIST Application (Abstract)

Douglas Kay , Santa Clara University
Samiha Mourad , Santa Clara University
pp. 0009

Robust and Low-Cost BIST Architectures for Sequential Fault Testing in Datapath Multipliers (Abstract)

M. Psarakis , University of Athens
A. Paschalis , University of Athens
N. Kranitis , University of Athens
D. Gizopoulos , University of Piraeus
Y. Zorian , LogicVision Inc.
pp. 0015
Session 2: Diagnosis Methods

Diagnosis of Tunneling Opens (Abstract)

James C.-M. Li , Stanford University
E.J. McCluskey , Stanford University
pp. 0022

On Diagnosing Path Delay Faults in an At-Speed Environment (Abstract)

Ramesh C. Tekumalla , Intel Corporation
Srikanth Venkataraman , Intel Corporation
Jayabrata Ghosh-Dastidar , University of Texas
pp. 0028

On Improving the Accuracy Of Multiple Defect Diagnosis (Abstract)

Shi-Yu Huang , National Tsing-Hua University
pp. 0034
Session 3: Test Data Compression

Design of Parameterizable Error-Propagating Space Compactors for Response Observation (Abstract)

A. Morosov , Potsdam University
M. Gossel , Potsdam University
K. Chakrabarty , Duke University
B. Bhattacharya , Indian Statistical Institute
pp. 0048

A Geometric-Primitives-Based Compression Scheme for Testing Systems-on-a-Chip (Abstract)

Aiman El-Maleh , King Fahd University of Petroleum and Minerals
Esam Khan , King Fahd University of Petroleum and Minerals
Saif al Zahir , University of British Columbia
pp. 0054
Session 4: Sythesis & Design for Testability

Testable Sequential Circuit Design: A Partition and Resynthesis Approach (Abstract)

Richard M. Chou , LSI Logic Corp.
Kewal K. Saluja , University of Wisconsin-Madison
pp. 0062

Breaking Correlation to Improve Testability (Abstract)

Kelly Ockunzzi , Case Western Reserve University
Chris Papachristou , Case Western Reserve University
pp. 0075
Session 5: Scan Chain Design

Multiple Scan Chain Design for Two-Pattern Testing (Abstract)

llia Polian , Institute of Computer Science
Bernd Becker , Albert-Ludwigs-University
pp. 0088
Session 6: Innovative Measurement Techniques

A Method for Measuring the Cycle-to-Cycle Period Jitter of High-Frequency Clock Signals (Abstract)

Takahiro J. Yamaguchi , Advantest Laboratories, Ltd
Masahiro Ishida , Advantest Laboratories, Ltd
Mani Soma , University of Washington
David Halter , Motorola Inc.
Rajesh Raina , Motorola Inc.
Jim Nissen , Motorola Inc.
pp. 0102

Built-In-Chip Testing of Voltage Overshoots in High-Speed SoCs (Abstract)

Amir Attarha , The University of Texas at Dallas
Mehrdad Nourani , The University of Tehran
pp. 0111

Current Measurement for Dynamic Idd Test (Abstract)

Xiaoyun Sun , University of Minnesota
Bapiraju Vinnakota , University of Minnesota
pp. 0117
Session 7: Diagnosis & Verification ATPG

Fault Equivalence Identification Using Redundancy Information and Static and Dynamic Extraction (Abstract)

M. Enamul Amyeen , Purdue University
W. Kent Fuchs , Purdue University
Irith Pomeranz , Purdue University
Vamsi Boppana , Fujitsu Labs of America
pp. 0124

Semi-Formal Test Generation for a Block of Industrial DSP (Abstract)

Julia Dushina , STMicroelectronics
Mike Benjamin , STMicroelectronics
Daniel Geist , IBM Haifa Research Lab
pp. 0131
Session 8: Defect Analysis and IDDx Diagnosis

Resistive Opens in a Class of CMOS Latches: Analysis and DFT (Abstract)

Antonio Zenteno , National Institute for Astrophysics, Optics and Electronics-INAOE
Victor H. Champac , National Institute for Astrophysics, Optics and Electronics-INAOE
pp. 0138

A Process and Technology-Tolerant IDDQ Method for IC Diagnosis (Abstract)

Chintan Patel , University of Maryland Baltimore County
Jim Plusquellic , University of Maryland Baltimore County
pp. 0145
Special Session 1: Panel
Special Session 2: Hot Topic Session
Session 9: SOC Testing

Socillator Test: A Delay Test Scheme for Embedded ICs in the Boundary-Scan Environment (Abstract)

Tek Jau Tan , National Chiao Tung University
Chung Len Lee , National Chiao Tung University
pp. 0158

Novel Spectral Methods for Built-In Self-Test in a System-on-a-Chip Environment (Abstract)

Ashish Giani , Intel Corporation
Shuo Sheng , Rutgers University
Michael S. Hsiao , Rutgers University
V. Agrawal , Bell Labs
pp. 0163
Session 10: Online Testing

Early Error Detection in Systems-on-Chip for Fault-Tolerance and At-Speed Debugging (Abstract)

E.S. Sogomonyan , Russian Academy of Science
A. Morosov , Potsdam University
J. Rzeha , Potsdam University
M. Gossel , Potsdam University
A. Singh , Auburn University
pp. 0184
Session 11: Self-Test Techniques

A Self-Test Methodology for IP Cores in Bus-Based Programmable SoCs (Abstract)

Jing-Reng Huang , University of California, Santa Barbara
Madhu K. Iyer , University of California, Santa Barbara
Kwang-Ting Cheng , University of California, Santa Barbara
pp. 0198

Embedded-Software-Based Approach to Testing Crosstalk-Induced Faults at On-Chip Buses (Abstract)

Wei-Cheng Lai , University of California, Santa Barbara
Jing-Reng Huang , University of California, Santa Barbara
Kwang-Ting (Tim) Cheng , University of California, Santa Barbara
pp. 0204

Electrically Induced Stimuli For MEMS Self-Test (Abstract)

Benoît Charlot , TIMA laboratory
Salvador Mir , TIMA laboratory
Fabien Parrain , TIMA laboratory
Bernard Courtois , TIMA laboratory
pp. 0210
Session 12: Memory Testing

Flash Memory Disturbances: Modeling and Test (Abstract)

Mohammad Gh. Mohammad , University of Wisconsin
Kewal K. Saluja , University of Wisconsin
pp. 0218

Efficient Neighborhood Pattern-Sensitive Fault Test Algorithms for Semiconductor Memories (Abstract)

Kuo-Liang Cheng , National Tsing Hua University
Ming-Fu Tsai , National Tsing Hua University
Cheng-Wen Wu , National Tsing Hua University
pp. 0225

An Efficient Methodology for Generating Optimal and Uniform March Tests (Abstract)

Sultan M. Al-Harbi , University of Southern California
Sandeep K. Gupta , University of Southern California
pp. 0231
Session 13: Scalable Fault Simulation, Model Build and ATPG Methods

RT-level Fault Simulation Based on Symbolic Propagation (Abstract)

Ozgur Sinanoglu , University of California, San Diego
Alex Orailoglu , University of California, San Diego
pp. 0240

Efficient Transparency Extraction and Utilization in Hierarchical Test (Abstract)

Yiorgos Makris , Yale University
Vishal Patel , University of California, San Diego
Alex Orailoglu , University of California, San Diego
pp. 0246
Session 14: Test Stimulus Generation for Analog Testing

Test Waveform Shaping in Mixed Signal Test Bus by Pre-Equalization (Abstract)

Yue-Tsang Chen , Chung Shan Institute of Science and Technology
Chauchin Su , National Central University
pp. 0260

A Low-Cost Adaptive Ramp Generator for Analog BIST Applications (Abstract)

F. Azaïs , University of Montpellier
S. Bernard , University of Montpellier
Y. Bertrand , University of Montpellier
X. Michel , University of Montpellier
M. Renovell , University of Montpellier
pp. 0266

Self-Testable Pipelined ADC with Low Hardware Overhead (Abstract)

Eduardo J. Peralías , Universidad de Sevilla
Gloria Huertas , Universidad de Sevilla
Adoración Rueda , Universidad de Sevilla
José L. Huertas , Universidad de Sevilla
pp. 0272
Special Session 3: Hot Topic Session
Special Session 4: Embedded Tutorial
Special Session 5: Panel
Session 15: Memory Diagnosis

Defect Oriented Fault Diagnosis for Semiconductor Memories using Charge Analysis: Theory and Experiments (Abstract)

I. de Paúl , University Illes Balears
M. Rosales , University Illes Balears
B. Alorda , University Illes Balears
J. Segura , University Illes Balears
C. Hawkins , The University of New Mexico
J. Soden , Sandia National Labs
pp. 0286

Enabling Embedded Memory Diagnosis via Test Response Compression (Abstract)

John T. Chen , Carnegie Mellon University
Wojciech Maly , Carnegie Mellon University
Janusz Rajski , Mentor Graphics Corporation
Omar Kebichi , Mentor Graphics Corporation
Jitendra Khare , Intel Corporation-Sacramento
pp. 0292

Automatic Generation of Diagnostic March Tests (Abstract)

Dirk Niggemeyer , University of Illinois
Elizabeth M. Rudnick , University of Illinois
pp. 0299
Session 16: Minimizing Test Power

Test Scheduling for Minimal Energy Consumption under Power Constraints (Abstract)

Tobias Schuele , University of Karlsruhe
Albrecht P. Stroele , University of Karlsruhe
pp. 0312
Session 17: Estimating and Reducing Infant Mortality

MINVDD Testing for Weak CMOS ICs (Abstract)

Chao-Wen Tseng , Stanford University
Ray Chen , Stanford University
Edward J. McCluskey , Stanford University
Phil Nigh , IBM MicroElectronics
pp. 0339
Session 18: Novel ATPG Techniques

SPIRIT: A Highly Robust Combinational Test Generation Algorithm (Abstract)

Emil Gizdarski , University of Rousse
Hideo Fujiwara , Nara Institute of Science and Technology
pp. 0346

Test Generation for Maximizing Ground Bounce for Internal Circuitry with Reconvergent Fan-outs (Abstract)

Yi-Shing Chang , University of Southern California
Sandeep Gupta , University of Southern California
Melvin Breuer , University of Southern California
pp. 0358
Session 19: Test Scheduling, Leakage Estimation and Onchip Delay Measurement

Average Leakage Current Estimation of CMOS Logic Circuits (Abstract)

José Pineda de Gyvez , Philips Research Labs
Eric van de Wetering , Philips Semiconductors
pp. 0375

An On-Chip Short-Time Interval Measurement Technique for Testing High-Speed Communication Links (Abstract)

Jiun-Lang Huang , University of California, Santa Barbara
Kwang-Ting Cheng , University of California, Santa Barbara
pp. 0380
Session 20: Fault Modeling and BIST Evaluation

Tools for the Characterization of Bipolar CML Testability (Abstract)

Ginette Monté , Ecole Polytechnique de Montr?al
Bernard Antaki , Ecole Polytechnique de Montr?al
Serge Patenaude , Ecole Polytechnique de Montr?al
Yvon Savaria , Ecole Polytechnique de Montr?al
Claude Thibeault , Ecole de Technologie Sup?rieure de Montr?al
Pieter Trouborst , Nortel Networks
pp. 0388

Testing of Dynamic Logic Circuits Based on Charge Sharing (Abstract)

Keerthi Heragu , Texas Instruments Inc.
Manish Sharma , University of Illinois
Rahul Kundu , Carnegie Mellon University
R.D. (Shawn) Blanton , Carnegie Mellon University
pp. 0396

An Evaluation of Pseudo Random Testing for Detecting Real Defects (Abstract)

Chao-Wen Tseng , Stanford University
Subhasish Mitra , Stanford University
Edward J. McCluskey , Stanford University
Scott Davidson , Sun Microsystems
pp. 0404
Special Session 6: Showcase
Special Session 7: Panel
Special Session 8: Panel

Author Index (PDF)

pp. 0416
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