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2013 IEEE 31st VLSI Test Symposium (VTS) (2000)
Montreal, Canada
Apr. 30, 2000 to May 4, 2000
ISSN: 1093-0167
ISBN: 0-7695-0613-5
TABLE OF CONTENTS

Foreword (PDF)

pp. xiii

Reviewers (PDF)

pp. xxvii
Plenary Session
Session 1: Microprocessor Test/Validation

Validation of PowerPC(tm) Custom Memories using Symbolic Simulation (Abstract)

Narayanan Krishnamurthy , Motorola ASP Somerset Design Center
Andrew K. Martin , Motorola ASP Somerset Design Center
Magdy S. Abadir , Motorola ASP Somerset Design Center
Jacob A. Abraham , University of Texas at Austin
pp. 9

On Testing the Path Delay Faults of a Microprocessor Using its Instruction Set (Abstract)

Wei-Cheng Lai , University of California at Santa Barbara
Angela Krstic , University of California at Santa Barbara
Kwang-Ting (Tim) Cheng , University of California at Santa Barbara
pp. 15
Session 2: Low Power BIST and Scan

Low Power/Energy BIST Scheme for Datapaths (Abstract)

D. Gizopoulos , University of Piraeus
N. Kranitis , II&T, NCSR ?Demokritos?
M. Psarakis , II&T, NCSR ?Demokritos?
A Paschalis , University of Athens
Y. Zorian , LogicVision
pp. 23

Low Power BIST via Non-Linear Hybrid Cellular Automata (Abstract)

Fulvio Corno , Politecnico di Torino
Maurizio Rebaudengo , Politecnico di Torino
Matteo Sonza Reorda , Politecnico di Torino
Giovanni Squillero , Politecnico di Torino
Massimo Violante , Politecnico di Torino
pp. 29

Static Compaction Techniques to Control Scan Vector Power Dissipation (Abstract)

Ranganathan Sankaralingam , University of Texas at Austin
Rama Rao Oruganti , University of Texas at Austin
Nur A. Touba , University of Texas at Austin
pp. 35
Session 3: Technology Trends and Their Impact on Test

Silicon-on-Insulator Technology Impacts on SRAM Testing (Abstract)

R. Dean Adams , International Business Machines
Phil Shephard Iii , International Business Machines
pp. 43
Session 4: Scan Related Approaches

BSM2: Next Generation Boundary-Scan Master (Abstract)

Frank P. Higgins , Bell Laboratories, Lucent Technologies
Rajagopalan Srinivasan , Bell Laboratories, Lucent Technologies
pp. 67

Virtual Scan Chains: A Means for Reducing Scan Length in Cores (Abstract)

Abhijit Jas , University of Texas at Austin
Bahram Pouya , University of Texas at Austin
Nur A. Touba , University of Texas at Austin
pp. 73
Session 5: Defect Driven Techniques

A Framework to Minimize Test Escape and Yield Loss during IDDQ Testing: A Case Study (Abstract)

Hugo Cheung , Burr-Brown Corporation
Sandeep K. Gupta , University of Southern California
pp. 89

Path Selection for Delay Testing of Deep Sub-Micron Devices Using Statistical Performance Sensitivity Analysis (Abstract)

Jing-Jia Liou , University of California at Santa Barbara
Kwang-Ting Cheng , University of California at Santa Barbara
Deb Aditya Mukherjee , Intel Corporation
pp. 97

PROBE: A PPSFP Simulator for Resistive Bridging Faults (Abstract)

Chul Young Lee , Compaq Computer Corporation
D.M.H. Walker , Texas A&M University
pp. 105
Session 6: System-on-chip Test Techniques

Test and Debug of Networking SoCs: A Case Study (Abstract)

A. Bommireddy , Level One Communications
J. Khare , Level One Communications
S. Shaikh , Level One Communications
S-T. Su , Level One Communications
pp. 121
Session 7: Analog Test Techniques

Test Generation for Accurate Prediction of Analog Specifications (Abstract)

Ram Voorakaranam , Georgia Institute of Technology
Abhijit Chatterjee , Georgia Institute of Technology
pp. 137

A Comprehensive TDM Comparator Scheme for Effective Analysis of Oscillation-Based Test (Abstract)

Jeongjin Roh , University of Texas at Austin
Jacob A. Abraham , University of Texas at Austin
pp. 143

Test Selection Based on High Level Fault Simulation for Mixed-Signal Systems (Abstract)

Sule Ozev , University of California at San Diego
Alex Orailoglu , University of California at San Diego
pp. 149
Session 8: BIST: Arithmetic, Memories and ILAs

Synthesis for Arithmetic Built-In Self-Test (Abstract)

Albrecht P. Stroele , University of Karlsruhe
pp. 165
SPECIAL SESSION 2: Embedded Tutorial
Session 9: Temperature and Process Drift Issues

Cold Delay Defect Screening (Abstract)

Chao-Wen Tseng , Stanford University
Edward J. McCluskey , Stanford University
Xiaoping Shao , Intel Corporation
David M. Wu , Intel Corporation
pp. 183

Thermal Testing: Fault Location Strategies (Abstract)

J. Altet , Polytechnical University of Catalonia (UPC)
A. Rubio , Polytechnical University of Catalonia (UPC)
E. Schaub , Universite Bordeaux 1
S. Dialhaire , Universite Bordeaux 1
W. Claeys , Universite Bordeaux 1
pp. 189

Detection of CMOS Defects under Variable Processing Conditions (Abstract)

Amy Germida , University of Maryland at Baltimore County
James Plusquellic , University of Maryland at Baltimore County
pp. 195
Session 10: Test Compaction and Design Validation

SIFAR: Static Test Compaction for Synchronous Sequential Circuits Based on Single Fault Restoration (Abstract)

Xijiang Lin , Mentor Graphics Corporation
Wu-Tung Cheng , Mentor Graphics Corporation
Irith Pomeranz , University of Iowa
Sudhakar M. Reddy , University of Iowa
pp. 205

ESIM: A Multimodel Design Error and Fault Simulator for Logic Circuits (Abstract)

Hussain Al-Asaad , University of California at Davis
John P. Hayes , University of Michigan
pp. 221
Session 11: Analog BIST

An Effective Defect-Oriented BIST Architecture for High-Speed Phase-Locked Loops (Abstract)

Seongwon Kim , University of Washington
Mani Soma , University of Washington
Dilip Risbud , National Semiconductor Corp.
pp. 231

Characterization of a Pseudo-Random Testing Technique for Analog and Mixed-Signal Built-in-Self-Test (Abstract)

Jan Arild Tofte , Mentor Graphics Corporation
Chee-Kian Ong , University of California at Santa Barbara
Jiun-Lang Huang , University of California at Santa Barbara
Kwang-Ting (Tim) Cheng , University of California at Santa Barbara
pp. 237

Hardware Resource Minimization for Histogram-Based ADC BIST (Abstract)

M. Renovell , Universit? de Montpellier II
F. Azaïs , Universit? de Montpellier II
S. Bernard , Universit? de Montpellier II
Y. Bertrand , Universit? de Montpellier II
pp. 247
Session 12: Functional Test and Verification Issues

DEFUSE: A Deterministic Functional Self-Test Methodology for Processors (Abstract)

Li Chen , University of California at San Diego
Sujit Dey , University of California at San Diego
pp. 255

Testing, Verification, and Diagnosis in the Presence of Unknowns (Abstract)

A. Jain , Intel Corp.
V. Boppana , Fujitsu Labs. of America, Inc.
R. Mukherjee , Fujitsu Labs. of America, Inc.
J. Jain , Fujitsu Labs. of America, Inc.
M. ~Fujita , Fujitsu Labs. of America, Inc.
M. Hsiao , Rutgers University
pp. 263
Session 13: Memory Test

Functional Memory Faults: A Formal Notation and a Taxonomy (Abstract)

Ad J. van de Goor , Delft University of Technology
Zaid Al-Ars , Delft University of Technology
pp. 281

Simulation-Based Test Algorithm Generation for Random Access Memories (Abstract)

Chi-Feng Wu , National Tsing Hua University
Chih-Tsun Huang , National Tsing Hua University
Kuo-Liang Cheng , National Tsing Hua University
Cheng-Wen Wu , National Tsing Hua University
pp. 291

Detection of Inter-Port Faults in Multi-Port Static RAMs (Abstract)

J. Zhao , Texas A&M University
S. Irrinki , LSI Logic Inc.
M. Puri , LSI Logic Inc.
F. Lombardi , Northeastern University
pp. 297
Session 14: Open Defect Detection, Diagnosis and Analog BIST

Detectability Conditions for Interconnection Open Defects (Abstract)

Victor H. Champac , National Institute for Astrophysics, Optics and Electronics
Antonio Zenteno , National Institute for Astrophysics, Optics and Electronics
pp. 305

Fault Detection Methodology and BIST Method for 2nd Order Butterworth, Chebyshev and Bessel Filter Approximations (Abstract)

José Vicente Calvano , Brazilian Navy Research Institute
Vladimir Castro Alves , Federal University. of Rio de Janeiro
Marcelo Lubaszewski , Federal University of Rio Grande do Sul
pp. 319
SPECIAL SESSION 3: Open Projector
SPECIAL SESSION 5: Panel

Biomedical ICs: What is Different about Testing those ICs? (PDF)

B. Vinnakota , University of Minnesota
Andre Ivanov , University of British Columbia
pp. 329
Session 15: Delay Test, Diagnosis and BIST

Bounding Circuit Delay by Testing a Very Small Subset of Paths (Abstract)

Manish Sharma , University of Illinois at Urbana-Champaign
Janak H. Patel , University of Illinois at Urbana-Champaign
pp. 333

A Low-Speed BIST Framework for High-Performance Circuit Testing (Abstract)

H.G. Kerkhoff , University of Twente
M. Shashaani , University of Waterloo
M. Sachdev , University of Waterloo
pp. 349
Session 16: BIST Issues

Hidden Markov and Independence Models with Patterns for Sequential BIST (Abstract)

Laurent Brehelin , Laboratoire d'Informatique, de Robotique et de Microelectronique de Montpellier
Olivier Gascuel , Laboratoire d'Informatique, de Robotique et de Microelectronique de Montpellier
Gilles Caraux , Laboratoire d'Informatique, de Robotique et de Microelectronique de Montpellier
Patrick Girard , Laboratoire d'Informatique, de Robotique et de Microelectronique de Montpellier
Christian Landrault , Laboratoire d'Informatique, de Robotique et de Microelectronique de Montpellier
pp. 359

Reducing Test Application Time for Built-in-Self-Test Test Pattern Generators (Abstract)

Ilker Hamzaoglu , University of Illinois at Urbana-Champaign
Janak H. Patel , University of Illinois at Urbana-Champaign
pp. 369

Linear Independence as Evaluation Criterion for Two-Dimensional Test Pattern Generators (Abstract)

Grzegorz Mrugalski , Poznan University of Technology
Jerzy Tyszer , Poznan University of Technology
Janusz Rajski , Mentor Graphics Corporation
pp. 377
Session 17: STIL Extension, Jitter, and Crosstalk

P1450.1: STIL for the Simulation Environment (Abstract)

Peter Wohl , Synopsys Inc.
Nathan Biggs , Priority Technologies Inc.
pp. 389

Extraction of Peak-to-Peak and RMS Sinusoidal Jitter Using an Analytic Signal Method (Abstract)

Takahiro J. Yamaguchi , Advantest Laboratories, Ltd.
Masahiro Ishida , Advantest Laboratories, Ltd.
Mani Soma , University of Washington
Toshifumi Watanabe , Advantest Corporation
Tadahiro Ohmi[4] , Tohoku Universityapan
pp. 395

Crosstalk Effect Removal for Analog Measurement in Analog Test Bus (Abstract)

Chauchin Su , National Central University
Yue-Tsang Chen , National Central University
pp. 403
Session 18: High Level ATPG and Test Scheduling

High-Level Observability for Effective High-Level ATPG (Abstract)

Fulvio Corno , Politecnico di Torino
Matteo Sonza Reorda , Politecnico di Torino
Giovanni Squillero , Politecnico di Torino
pp. 411

The Left Edge Algorithm and the Tree Growing Technique in Block-Test Scheduling under Power Constraints (Abstract)

Valentin Muresan , Dublin City University
Xiaojun Wang , Dublin City University
Valentina Muresan , University of Timisoara
Mircea Vladutiu , University of Timisoara
pp. 417

Testability Alternatives Exploration through Functional Testing (Abstract)

F. Ferrandi , Politecnico di Milano
G. Fornara , Politecnico di Milano
D. Sciuto , Politecnico di Milano
G. Ferrara , Siemens Information and Communication Networks
F. Fummi , Universit? di Verona
pp. 423
Session 19: IDDQ Test

Delta Iddq for Testing Reliability (Abstract)

Theo J. Powell , Texas Instruments, Inc.
James Pair , Texas Instruments, Inc.
Melissa St. John , Texas Instruments, Inc.
Doug Counce , Texas Instruments, Inc.
pp. 439

Clustering Based Evaluation of IDDQ Measurements: Applications in Testing and Classification of ICs (Abstract)

Sri Jandhyala , Texas Instruments Inc.
Hari Balachandran , Texas Instruments Inc.
Manidip Sengupta , Texas Instruments Inc.
Anura P. Jayasumana , Colorado State University
pp. 444
Session 20: On-line Testing and Fault Tolerance

Fault Escapes in Duplex Systems (Abstract)

Subhasish Mitra , Stanford University
Nirmal R. Saxena , Stanford University
Edward J. McCluskey , Stanford University
pp. 453

Invariance-Based On-Line Test for RTL Controller-Datapath Circuits (Abstract)

Yiorgos Makris , University of California at San Diego
Ismet Bayraktaroglu , University of California at San Diego
Alex Orailoglu , University of California at San Diego
pp. 459
SPECIAL SESSION 7: Panel

Do I Need this Tool for My Chips to Work? (PDF)

F. Muradali , Agilent Technologies
A. Ivanov , University of British Columbia
pp. 471
SPECIAL SESSION 8: Panel

Author Index (PDF)

pp. 475
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