Proceedings 18th IEEE VLSI Test Symposium (2000)
Apr. 30, 2000 to May 4, 2000
Ilker Hamzaoglu , University of Illinois at Urbana-Champaign
Janak H. Patel , University of Illinois at Urbana-Champaign
This paper presents a new technique, called C-compatibility, for reducing the test application time of the counter-based exhaustive Built-in-Self-Test (BIST) test pattern generators. This technique reduces the test application time by reducing the size of the binary counter used in the test pattern generators. We have incorporated the synthesis algorithm for synthesizing BIST test pattern generators using the C-compatibility technique into ATOM, an advanced ATPG system for combinational circuits. The experimental results showed that the test pattern generators synthesized using this technique for the ISCAS85 and full scan versions of the ISCAS89 benchmark circuits achieve 100% stuck-at fault coverage in much smaller test application time than the previously published counter-based exhaustive BIST test pattern generators.
Built-in-Self-Test, Test Application Time, Test Generation, Stuck-at Fault Model, Combinational Circuits
J. H. Patel and I. Hamzaoglu, "Reducing Test Application Time for Built-in-Self-Test Test Pattern Generators," Proceedings 18th IEEE VLSI Test Symposium(VTS), Montreal, Canada, 2000, pp. 369.