Proceedings 18th IEEE VLSI Test Symposium (2000)
Apr. 30, 2000 to May 4, 2000
A. Jain , Intel Corp.
V. Boppana , Fujitsu Labs. of America, Inc.
R. Mukherjee , Fujitsu Labs. of America, Inc.
J. Jain , Fujitsu Labs. of America, Inc.
M. ~Fujita , Fujitsu Labs. of America, Inc.
M. Hsiao , Rutgers University
Improvement of the accuracy of error and fault diagnosis as well as ATPG for IP-based designs is important problems in industry. In this paper, we address these problems when portions of the design may be unspecified. Two approaches to solve these problems have been presented: (1) solving Boolean satisfiability under unknown constraints, and (2) a network modification-based solution. Experimental results on constrained equivalence checking, enhancement of error diagnosis resolution for combinational circuits, and ATPG for IP-based designs have been presented on the ISCAS 85 benchmark and industrial circuits.
V. Boppana, A. Jain, J. Jain, M. Hsiao, R. Mukherjee and M. ~Fujita, "Testing, Verification, and Diagnosis in the Presence of Unknowns," Proceedings 18th IEEE VLSI Test Symposium(VTS), Montreal, Canada, 2000, pp. 263.