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2013 IEEE 31st VLSI Test Symposium (VTS) (2000)
Montreal, Canada
Apr. 30, 2000 to May 4, 2000
ISSN: 1093-0167
ISBN: 0-7695-0613-5
pp: 247
M. Renovell , Universit? de Montpellier II
Y. Bertrand , Universit? de Montpellier II
F. Azaïs , Universit? de Montpellier II
S. Bernard , Universit? de Montpellier II
The paper proposes a BIST approach for deriving the main characterization parameters of ADCs from histogram data. An adequate choice of input stimulus and time decomposition scheme is proposed in order to minimize the extra on-chip hardware required to extract these parameters. The idea of time decomposition consists in replacing classical hardware-consuming concurrent calculations by hardware-saving time-spread calculations. The decomposition technique is used both at high level (specific test phases are dedicated to each ADC parameter computation) and low level (sequential steps inside each test phase). Pseudo-algorithms are given to derive offset, gain error and non-linearities.
M. Renovell, Y. Bertrand, F. Azaïs, S. Bernard, "Hardware Resource Minimization for Histogram-Based ADC BIST", 2013 IEEE 31st VLSI Test Symposium (VTS), vol. 00, no. , pp. 247, 2000, doi:10.1109/VTEST.2000.843852
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