The Community for Technology Leaders
2013 IEEE 31st VLSI Test Symposium (VTS) (1999)
San Diego, California
Apr. 26, 1999 to Apr. 30, 1999
ISSN: 1093-0167
ISBN: 0-7695-0146-X
TABLE OF CONTENTS

Foreword (PDF)

pp. xiii

Program Committee (PDF)

pp. xviii

Reviewers (PDF)

pp. xxii
Keynote Address
Invited Presentation
Session 1: Testing High-Speed and Dynamic Circuits: Moderators: B. Courtois, TIMA
Session 2: Core Testing: Moderators: R. Garcia, Schlumberger

Instruction Randomization Self Test For Processor Cores (Abstract)

Ken Batcher , Case Western Reserve University
Christos Papachristou , Case Western Reserve University
pp. 34

A New Totally Error Propagating Compactor for Arbitrary Cores with Digital Interfaces (Abstract)

M. Gössel , University of Potsdam
E.S. Sogomonyan , Russian Academy of Science
A. Morosov , University of Potsdam
pp. 49
Session 3: Diagnosis: Moderators: R. Galivanche, Intel

Multiple Design Error Diagnosis and Correction in Digital VLSI Circuits (Abstract)

Srikanth Venkataraman , Intel Corporation
Andreas Veneris , University of Illinois at Urbana
W. Kent Fuchs , Purdue University
Ibrahim N. Hajj , University of Illinois at Urbana
pp. 58
Session 4: Techniques for the Very-Deep Submicron: Moderators: L. Bouzaida, ST Microelectronics

Using Temporal Constraints for Eliminating Crosstalk Candidates for Design and Test (Abstract)

Michael A. Margolese , University of California, at Santa Cruz
F. Joel Ferguson , University of California, at Santa Cruz
pp. 80

Test Generation for Ground Bounce in Internal Logic Circuitry (Abstract)

Melvin A. Breuer , University of Southern California
Sandeep K. Gupta , University of Southern California
Yi-Shing Chang , University of Southern California
pp. 95
Session 5: Advanced Scan Path Techniques: Moderators: K. Ruparel, Cisco

Scan Vector Compression/Decompression Using Statistical Coding (Abstract)

Jayabrata Ghosh-Dastidar , University of Texas at Austin
Nur A. Touba , University of Texas at Austin
Abhijit Jas , University of Texas at Austin
pp. 114

Partial Scan Using Multi-Hop State Reachability Analysis (Abstract)

Michael S. Hsiao , Rutgers University
Sameer Sharma , Rutgers University
pp. 121
Session 6: IDDQ Testing: Moderators: C. Hawkins, University of New Mexico

On the Comparison of IDDQ and IDDQ Testing (Abstract)

C. Thibeault , ?cole de Technologie Sup?rieure
pp. 143
Session 7: Delay Fault Testing: Moderators: J. Aylor, University of Virginia

Delay Fault Testing of Designs with Embedded IP Cores (Abstract)

John P. Hayes , University of Michigan
Hyungwon Kim , University of Michigan
pp. 160

Adaptive Techniques for Improving Delay Fault Diagnosis (Abstract)

Nur A. Touba , University of Texas at Austin
Jayabrata Ghosh-Dastidar , University of Texas at Austin
pp. 168
Session 8: Validation, Verification, and Diagnosis: Moderators: D. Pradhan, Texas A&M University

Verification of Processor Microarchitectures (Abstract)

Jacob A. Abraham , The University of Texas at Austin
Jian Shen , The University of Texas at Austin
pp. 189

Techniques to Encode and Compress Fault Dictionaries (Abstract)

Sreejit Chakravarty , Intel Corporation
Vinodh Gopal , Compaq Computer Corp.
pp. 195

Implication and Evaluation Techniques for Proving Fault Equivalence (Abstract)

W. Kent Fuchs , Purdue University
Irith Pomeranz , University of Iowa
Vamsi Boppana , Fujitsu Labs of America
M. Enamul Amyeen , Purdue University
pp. 201
Session 9: Mixed Signal Testing: Moderators: G. Roberts, McGill University

Efficient Test Generation for Transient Testing of Analog Circuits Using Partial Numerical Simulation (Abstract)

Pramodchandran N. Variyam , Georgia Institute of Technology
Abhijit Chatterjee , Georgia Institute of Technology
Junwei Hou , Georgia Institute of Technology
pp. 214

Specification Back-Propagation and Its Application to DC Fault Simulation for Analog/Mixed-Signal Circuits (Abstract)

Jiun-Lang Huang , University of California at Santa Barbara
Kwang-Ting Cheng , University of California at Santa Barbara
Chen-Yang Pan , University of California at Santa Barbara
pp. 220
Session 10: BIST: Moderators: S. Wu, Lucent Bell Labs

Comparative Study of CA-based PRPGs and LFSRs with Phase Shifters (Abstract)

Jerzy Tyszer , Poznan University of Technology
Grzegorz Mrugalski , Poznan University of Technology
Janusz Rajski , Mentor Graphics Corporation
pp. 236

An Effective BIST Architecture for Sequential Fault Testing in Array Multipliers (Abstract)

Antonis Paschalis , NCSR "Demokritos"
Yervant Zorian , LogicVision, Inc.
Dimitris Gizopoulos , 4PLUS Technologies
Mihalis Psarakis , NCSR "Demokritos"
pp. 252
Session 11: ATPG Related Approaches: Moderators: J. Sprock, Synopsys

Procedures for Identifying Undetectable and Redundant Faults In Synchronous Sequential Circuits (Abstract)

Sudhakar M. Reddy , University of Iowa
Xijiang Lin , Mentor Graphics Corporation
Nadir Z. Basturkmen , University of Iowa
Irith Pomeranz , University of Iowa
pp. 275
Session 12: Testing MEMS, MCM and Analog Circuits: Moderators: D. Keezer, Georgia Tech

A Novel Test Methodology for MEMS Magnetic Micromotors (Abstract)

Bruce C. Kim , Michigan State University
Krishna Marella , Michigan State University
pp. 284

A New Bare Die Test Methodology (Abstract)

K.L. Tai , Bell Laboratories
Zao Yang , Silicon Graphics Inc.
K.-T. Cheng , University of California at Santa Barbara
pp. 290

Hierarchical Test Generation for Analog Circuits Using Incremental Test Development (Abstract)

Abhijit Chatterjee , Georgia Institute of Technology
Ramakrishna Voorakaranam , Georgia Institute of Technology
pp. 296
Session 13: Mixed Signal BIST: Moderators: B. Kaminska, Opmaxx

A Current Integrator for BIST of Mixed-Signal ICs (Abstract)

André Ivanov , University of British Columbia
Sassan Tabatabaei , University of British Columbia
pp. 311

A Test Point Insertion Algorithm for Mixed-Signal Circuits (Abstract)

Jinyan Zhang , University of Washington
Mani Soma , University of Washington
Sam Huynh , University of Washington
pp. 319
Session 14: High-Level Test Techniques: Moderators: K. Kinoshita, Osaka University

Behavioral Fault Modeling in a VHDL Synthesis Environment (Abstract)

Barry W. Johnson , University of Virginia
Ronald J. Hayne , University of Virginia
pp. 333

RT-level TPG Exploiting High-Level Synthesis Information (Abstract)

Paolo Prinetto , Polit?cnico di Torino
Silvia Chiusano , Polit?cnico di Torino
Fulvio Corno , Polit?cnico di Torino
pp. 341
Session 15: Concurrent Checking: Moderators: J. Huertas, Centro Nacional de Microelec
Session 16: Memory Test: Moderators: C.-W. Wu, Tsing Hua University

Maximal Diagnosis of Interconnects of Random Access Memories _ (Abstract)

Jun Zhao , Texas A&M University
Fred J. Meyer , Northeastern University
Fabrizio Lombardi , Northeastern University
pp. 378
Session 17: BIST Related Approaches: Moderators: R. David, Lab d'Automatique de Grenoble

A Test Vector Inhibiting Technique for Low Energy BIST Design (Abstract)

P. Girard , Universit? Montpellier
S. Pravossoudovitch , Universit? Montpellier
L. Guiller C. Landrault , Universit? Montpellier
pp. 407

Enhanced Bist-Based Diagnosis of FPGAs via Boundary Scan Access (Abstract)

Carter Hamilton , University of Kentucky
Sajitha Wijesuriya , University of Kentucky
Gretchen Gibson , University of Kentucky
Charles Stroud , University of Kentucky
pp. 413
Session 18: Defect Oriented Test: Moderators: Y. Malaiya, Colorado State University

Analyzing the Need for ATPG Targeting GOS Defects (Abstract)

E. Isern , Universit?t Illes Balears
J. Segura , Universit?t Illes Balears
M. Roca , Universit?t Illes Balears
pp. 420

On the Evaluation of Arbitrary Defect Coverage of Test Sets (Abstract)

Vamsi Boppana , Fujitsu Labs of America, Inc.
Ankur Jain , Rutgers University
M. Fujita , Fujitsu Labs of America, Inc.
Michael S. Hsiao , Rutgers University
pp. 426

Defect-Oriented Test Scheduling (Abstract)

Wanli Jiang , University of Minnesota
Bapiraju Vinnakota , University of Minnesota
pp. 433
Session 19: On-Line Testing and Fault Tolerance: Moderators: M. Bayoumi, University of Southwestern Louisiana

Low-Cost On-Line Test for Digital Filters (Abstract)

Alex Orailoglu , University of California at San Diego
Ismet Bayraktaroglu , University of California at San Diego
pp. 446
Session 20: DFT and Boundary Scan: Moderators: S. Mourad, Santa Clara University

A Systematic DFT Procedure for Library Cells (Abstract)

Rahul Kundu , University of California at Santa Cruz
Jingjing Xu , University of California at Santa Cruz
F. Joel Ferguson , University of California at Santa Cruz
pp. 460
Special Session 2: IEEE P1500: SOC Test Standardization: Moderator: K. Wagner, Stream Machine
Embedded Presentation: At-Speed Logic Built-In Self-Test: Moderator: J. Rajski, J. Tyszer

Author Index (PDF)

pp. 487
98 ms
(Ver )