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Proceedings 17th IEEE VLSI Test Symposium (Cat. No.PR00146) (1999)
San Diego, California
Apr. 26, 1999 to Apr. 30, 1999
ISSN: 1093-0167
ISBN: 0-7695-0146-X
pp: 341
Silvia Chiusano , Polit?cnico di Torino
Fulvio Corno , Polit?cnico di Torino
Paolo Prinetto , Polit?cnico di Torino
High-level test pattern generation is today a widely investigated research topic. The present paper proposes a fully automated, simulation-based ATPG system, to address test pattern generation for circuits described at the RT-level. The approach is based on a set of suitable testability metrics, and the test pattern generation phase resorts to Genetic Algorithms. Experiments show the excellent fault coverage provided by the RT-level test patterns, when applied at the final gate-level. The approach, being based on a high-level representation, promises to be particularly suited where gate-level ATPGs are often inefficient, mainly for large circuits and for control-intensive designs.

P. Prinetto, S. Chiusano and F. Corno, "RT-level TPG Exploiting High-Level Synthesis Information," Proceedings 17th IEEE VLSI Test Symposium (Cat. No.PR00146)(VTS), San Diego, California, 1999, pp. 341.
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