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For many years, non-target detection experiments have been simulated by using AND/OR bridges or gross delay faults as surrogates. For example, the defective part level can be estimated based upon surrogate detection when test patterns target stuck-at faults in the circuit. For the first time, test pattern generation techniques that attempt to maximize non-target defect detection have been used to test a real, 100% scanned, commercial chip consisting of 75K logic gates. In this experiment, the defective part level for REDO-based patterns was 1,288 parts per million lower than that achieved by DC stuck-at based patterns generated using today's state of the art tools and techniques.

V. Mathur et al., "REDO - Probabilistic Excitation and Deterministic Observation - First Commercial Experiment," Proceedings 17th IEEE VLSI Test Symposium (Cat. No.PR00146)(VTS), San Diego, California, 1999, pp. 268.
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