The Community for Technology Leaders
Proceedings. 16th IEEE VLSI Test Symposium (Cat. No.98TB100231) (1998)
Monterey, California
Apr. 26, 1998 to Apr. 30, 1998
ISSN: 1093-0167
ISBN: 0-8186-8436-4

Foreword (PDF)

pp. xiii

Advisory Board (PDF)

pp. xvii

Program Committee (PDF)

pp. xviii

Reviewers (PDF)

pp. xxiii
Invited Keynote Address
Session 1: Core and System on Chip Test: Moderators: Bernard Courtois, TIMA
Session 2: Testing Deep Submicron Circuits: Moderators: Vishwani D. Agrawal, Lucent Technologies
Session 3: Diagnosis and Validation: Moderators: Wayne Needham, Intel
Session 4: BIST 1: Moderators: Melvin A. Breuer, University of Southern California
Session 5: Scan & Boundary Scan: Moderators: Gordon Robinson, Credence Systems
Session 6: IDDQ and VLV Test: Moderators: Thomas W. Williams, Synopsys
Session 7: Analog Test: Moderators: Laroussi Bouzaida, SGS Thomson
Session 8: Sequential Test and Redundancy Removal: Moderators: Jim Aylor, University of Virginia
Embedded Tutorial 1
Session 9: Delay Fault Test: Moderators: Kenneth Butler, Texas Instruments
Session 10: BIST 2: Moderators: Shianling Wu, Lucent Technologies
Session 11: Testing High-Speed Circuits: Moderators: Robert Aitken, Hewlett-Packard
Session 12: Validation/Verification: Moderators: Barry Johnson, University of Virginia
Session 13: Defect Level Test: Moderators: Wojciech Maly, Carnegie Mellon University
Session 14: Concurrent Checking & Fault Tolerance: Moderators: David Keezer, Georgia Tech
Panel 1: Moderator/Coordinator: Y. Zorian, LogicVision
Panel and Embedded Tutorial 2: Moderator/Coordinator: Bernard Courtois, TIMA
Embedded Tutorial 3: Coordinator: Tim Cheng, University of California, Santa Barbara
Session 15: Scan Techniques: Moderators: Yashwant Malaiya, Colorado State University
Session 16: On-Line Testing: Moderators: Cecilia Metra, University of Bologna
Session 17: Analog/Mixed Signal Test and DFT: Moderators: Rene Segers, Philips
Session 18: Memory Test: Moderators: David Broster, European Commission
Session 19: BIST 3: Moderators: Kewal Saluja, University of Wisconsin
Session 20: New ATPG Techniques: Moderators: Rajesh Galivanche, Intel
Panel 3: Moderator: Theo Powell, Texas Instruments
Embedded Tutorial 4: Coordinator: Bozena Kaminska, OPMAXX
Panel 4: Moderator/Coordinator: Fidel Muradali, Hewlett-Packard

Author Index (PDF)

pp. 471
93 ms
(Ver 3.3 (11022016))