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2013 IEEE 31st VLSI Test Symposium (VTS) (1997)
Monterey, California
Apr. 27, 1997 to May 1, 1997
ISBN: 0-8186-7810-0
TABLE OF CONTENTS

Foreword (PDF)

pp. xiii

Reviewers (PDF)

pp. xix

Best Panel Award 96 (PDF)

pp. xxiii
KEYNOTE ADDRESS
INVITED TALK
SESSION 1: CORE & PROCESSOR TEST

Testing Embedded Cores Using Partial Isolation Rings (Abstract)

Bahram Pouya , University of Texas at Austin
Nur A. Touba , University of Texas at Austin
pp. 10

A practical approach to instruction-based test generation for functional modules of VLSI processors (Abstract)

K. Hatayama , Res. Lab., Hitachi Ltd., Ibaraki, Japan
H. Yamada , Res. Lab., Hitachi Ltd., Ibaraki, Japan
T. Miyazaki , Res. Lab., Hitachi Ltd., Ibaraki, Japan
K. Hikone , Res. Lab., Hitachi Ltd., Ibaraki, Japan
pp. 17
SESSION 2: RAM TEST

Assessing SRAM test coverage for sub-micron CMOS technologies (Abstract)

T. Chen , Colorado State University
V. Kim , Colorado State University
pp. 24

Experimental fault analysis of 1 Mb SRAM chips (Abstract)

K. Iwasaki , Fac. of Eng., Chiba Univ., Japan
H. Goto , Fac. of Eng., Chiba Univ., Japan
S. Nakamura , Fac. of Eng., Chiba Univ., Japan
pp. 31

Disturb Neighborhood Pattern Sensitive Fault (Abstract)

A.J. van de Goor , Delft University of Technology
I.B.S. Tlili , Delft University of Technology
pp. 37
SESSION 3: BIST I

Methods to reduce test application time for accumulator-based self-test (Abstract)

A.P. Stroele , Karlsruhe Univ., Germany
F. Mayer , Karlsruhe Univ., Germany
pp. 48

Implicit test pattern generation constrained to cellular automata embedding (Abstract)

D. Sciuto , Politecnico di Milano, Italy
F. Fummi , Politecnico di Milano, Italy
pp. 54

Cellular automata for deterministic sequential test pattern generation (Abstract)

F. Corno , Dipt. di Autom. e Inf., Politecnico di Torino, Italy
S. Chiusano , Dipt. di Autom. e Inf., Politecnico di Torino, Italy
P. Prinetto , Dipt. di Autom. e Inf., Politecnico di Torino, Italy
M. Sonza Reorda , Dipt. di Autom. e Inf., Politecnico di Torino, Italy
pp. 60
SESSION 4: CURRENT TESTING TECHNIQUES

Bridges in sequential CMOS circuits: current-voltage signature (Abstract)

J. Figueras , Dept. d'Enginyeria Electron., Univ. Politecnica de Catalunya, Barcelona, Spain
R. Rodriguez-Montanes , Dept. d'Enginyeria Electron., Univ. Politecnica de Catalunya, Barcelona, Spain
pp. 68

Using fault sampling to compute I/sub DDQ/ diagnostic test sets (Abstract)

Yiming Gong , Quickturn Syst. Inc., Mountain View, CA, USA
S. Chakravarty , Quickturn Syst. Inc., Mountain View, CA, USA
pp. 74

A novel probabilistic approach for IC diagnosis based on differential quiescent current signatures (Abstract)

C. Thibeault , Dept. of Electr. Eng., Ecole de Technol. Superieure, Montreal, Que., Canada
pp. 80
SESSION 5: DELAY TEST & DIAGNOSIS

High Quality Robust Tests for Path Delay Faults (Abstract)

Liang-Chi Chen , Electrical Engineering -- Systems University of Southern California, CA, USA
Melvin A. Breuer , Electrical Engineering -- Systems University of Southern California, CA, USA
Sandeep K. Gupta , Electrical Engineering -- Systems University of Southern California, CA, USA
pp. 88

An optimized BIST test pattern generator for delay testing (Abstract)

S. Pravossoudovitch , Univ. des Sci. et Tech. du Languedoc, Montpellier, France
P. Girard , Univ. des Sci. et Tech. du Languedoc, Montpellier, France
C. Landrault , Univ. des Sci. et Tech. du Languedoc, Montpellier, France
V. Moreda , Univ. des Sci. et Tech. du Languedoc, Montpellier, France
pp. 94

On the Fault Coverage of Interconnect Diagnosis (Abstract)

F. Lombardi , Texas A & M University
X.T. Chen , Texas A & M University
F.J. Meyer , Texas A & M University
pp. 101
SESSION 6: FAULT MODELING & PARAMETRIC TEST

Analysis of Ground Bounce in Deep Sub-Micron Circuits (Abstract)

Melvin A. Breuer , Electrical Engineering - Systems University of Southern California, Los Angeles
Sandeep K. Gupta , Electrical Engineering - Systems University of Southern California, Los Angeles
Yi-Shing Chang , Electrical Engineering - Systems University of Southern California, Los Angeles
pp. 110

Switch-level modeling of feedback faults using global oscillation control (Abstract)

P. Dahlgren , Dept. of Comput. Eng., Chalmers Univ. of Technol., Goteborg, Sweden
pp. 117

Built-in parametric test for controlled impedance I/Os (Abstract)

T. Haulin , Ericsson Telecom AB, Stockholm, Sweden
pp. 123
SESSION 7: VERIFICATION & DEBUGGING

Using ATPG for clock rules checking in complex scan designs (Abstract)

P. Wohl , Adv. Test Technol. Inc., Williston, VT, USA
J. Waicukauski , Adv. Test Technol. Inc., Williston, VT, USA
pp. 130

A Novel Solution for Chip-Level Functional Timing Verification (Abstract)

Rathish Jayabharathi , Design Technology - Logic Test Technology Intel Corporation, Folsom, CA
Kyung Tek Lee , Computer Engineering Research Center University of Texas at Austin, Austin, TX
Jacob A. Abraham , Computer Engineering Research Center University of Texas at Austin, Austin, TX
pp. 137

Incremental logic rectification (Abstract)

Kwang-Ting Cheng , Dept. of Electr. & Comput. Eng., California Univ., Santa Barbara, CA, USA
Shi-Yu Huang , Dept. of Electr. & Comput. Eng., California Univ., Santa Barbara, CA, USA
Kuang-Chien Chen , Dept. of Electr. & Comput. Eng., California Univ., Santa Barbara, CA, USA
pp. 143

Polynomial Formal Verification of Multipliers (Abstract)

Michael Martin , Institute of Computer Science Albert-Ludwigs-University
Bernd Becker , Institute of Computer Science Albert-Ludwigs-University
Rolf Drechsler , Institute of Computer Science Albert-Ludwigs-University
Martin Keim , Institute of Computer Science Albert-Ludwigs-University
Paul Molitor , Institute of Computer Science Albert-Ludwigs-University
pp. 150
SESSION 8: ANALOG TEST 1

Parametric and Catastrophic Fault Coverage of Analog Circuits in Oscillation-Test Methodology (Abstract)

Bozena Kaminska , Ecole Polytechnique de Montreal
Karim Arabi , OPMAX Engineering Inc. Beaverton (OR)
pp. 166

Extension of Inductive Fault Analysis to Parametric Faults in Analog Circuits with Application to Test Generation (Abstract)

Zbigniew Jaworski , Institute of Microelectronics and Optoelectronics Warsaw University of Technology zj@imio.pw.edu.pl, mn@imio.pw.edu.pl, wbk@imio.pw.edu.pl
Wieslaw Kuzmicz , Institute of Microelectronics and Optoelectronics Warsaw University of Technology zj@imio.pw.edu.pl, mn@imio.pw.edu.pl, wbk@imio.pw.edu.pl
Mariusz Niewczas , Institute of Microelectronics and Optoelectronics Warsaw University of Technology zj@imio.pw.edu.pl, mn@imio.pw.edu.pl, wbk@imio.pw.edu.pl
pp. 172

Behavioral level noise modeling and jitter simulation of phase-locked loops with faults using VHDL-AMS (Abstract)

N.J. Godambe , Dept. of Electr. & Comput. Eng., Iowa Univ., Iowa City, IA, USA
C.-J.R. Shi , Dept. of Electr. & Comput. Eng., Iowa Univ., Iowa City, IA, USA
pp. 177
PANEL SESSION 1:
PANEL SESSION 2
SESSION 9: SEQUENTIAL CIRCUITS TEST I

Fast Algorithms for Static Compaction of Sequential Circuit Test Vectors (Abstract)

Janak H. Patel , Center for Reliable and High-Performance Computing University of Illinois, Urbana, IL http://www.crhc.uiuc.edu/
Elizabeth M. Rudnick , Center for Reliable and High-Performance Computing University of Illinois, Urbana, IL http://www.crhc.uiuc.edu/
Michael S. Hsiao , Center for Reliable and High-Performance Computing University of Illinois, Urbana, IL http://www.crhc.uiuc.edu/
pp. 188

Critical hazard free test generation for asynchronous circuits (Abstract)

A. Khoche , Sunrise Test Syst., Fremont, CA, USA
E. Brunvand , Sunrise Test Syst., Fremont, CA, USA
pp. 203
SESSION 10: CONCURRENT CHECKING

Highly testable and compact single output comparator (Abstract)

B. Ricco , Dipt. di Elettronica Inf. e Sistemistica, Bologna Univ., Italy
C. Metra , Dipt. di Elettronica Inf. e Sistemistica, Bologna Univ., Italy
M. Favalli , Dipt. di Elettronica Inf. e Sistemistica, Bologna Univ., Italy
pp. 210

Self-exercising self testing k-order comparators (Abstract)

X. Kavousianos , Dept. of Comput. Eng. & Inf., Patras Univ., Greece
D. Nikolos , Dept. of Comput. Eng. & Inf., Patras Univ., Greece
pp. 216

Exact probabilistic analysis of error detection for parity checkers (Abstract)

V.A. Vardanian , Armenian Nat. Academy of Sci., American Univ. of Armenia, Yerevan, Armenia
pp. 222
SESSION 11: TEST OF REGULAR STRUCTURES

Test of RAM-based FPGA: methodology and application to the interconnect (Abstract)

M. Renovell , LIRMM-UM, Montpellier, France
Y. Zorian , LIRMM-UM, Montpellier, France
J. Figueras , LIRMM-UM, Montpellier, France
pp. 230

Robust Sequential Fault Testing of Iterative Logic Arrays (Abstract)

Antonis Paschalis , Institute of Informatics & Telecommunications, NCSR Athens, GREECE
Dimitris Gizopoulos , Institute of Informatics & Telecommunications, NCSR Athens, GREECE
Mihalis Psarakis , Institute of Informatics & Telecommunications, NCSR Athens, GREECE
pp. 238

A new approach for testing artificial neural networks (Abstract)

L.A. Belfore, II , Dept. of Electr. & Comput. Eng., Marquette Univ., Milwaukee, WI, USA
C.A. Fleischer , Dept. of Electr. & Comput. Eng., Marquette Univ., Milwaukee, WI, USA
pp. 245
SESSION 12: ANALOG TEST II

Test Synthesis for DC Test and Maximal Diagnosis of Switched-Capacitor Circuits (Abstract)

Hassan Ihs , Laboratoire d'Informatique de Robotique
Christian Dufaza , Laboratoire d'Informatique de Robotique
pp. 252

Low-cost and efficient digital-compatible BIST for analog circuits using pulse response sampling (Abstract)

N. Nagi , Sch. of Electr. Eng., Georgia Inst. of Technol., Atlanta, GA, USA
A. Chatterjeee , Sch. of Electr. Eng., Georgia Inst. of Technol., Atlanta, GA, USA
P.N. Variyam , Sch. of Electr. Eng., Georgia Inst. of Technol., Atlanta, GA, USA
pp. 261

Functional test pattern generation for CMOS operational amplifier (Abstract)

Chung Len Lee , Dept. of Electron. Eng., Nat. Chiao Tung Univ., Hsinchu, Taiwan
Soon Jyh Chang , Dept. of Electron. Eng., Nat. Chiao Tung Univ., Hsinchu, Taiwan
Jwu E Chen , Dept. of Electron. Eng., Nat. Chiao Tung Univ., Hsinchu, Taiwan
pp. 267
SESSION 13: FAULT SIMULATION AND REDUNDANCY IDENTIFICATION

SPITFIRE: scalable parallel algorithms for test set partitioned fault simulation (Abstract)

J.H. Patel , Center for Reliable & High Performance Comput., Illinois Univ., Urbana, IL, USA
D. Krishnaswamy , Center for Reliable & High Performance Comput., Illinois Univ., Urbana, IL, USA
E.M. Rudnick , Center for Reliable & High Performance Comput., Illinois Univ., Urbana, IL, USA
P. Banerjee , Center for Reliable & High Performance Comput., Illinois Univ., Urbana, IL, USA
pp. 274

The Dynamic Rollback Problem in Concurrent Event-Driven Fault Simulation (Abstract)

Pier Luca Montessoro , Dip. di Ingegneria Elettrica, Gestionale e Meccanica Universita` degli Studi di Udine
Laura Farinetti , Dip. di Automatica e Informatica, Politecnico di Torino
pp. 282

Static logic implication with application to redundancy identification (Abstract)

E.M. Rudnick , Center for Reliable & High Performance Comput., Illinois Univ., Urbana, IL, USA
J.H. Patel , Center for Reliable & High Performance Comput., Illinois Univ., Urbana, IL, USA
J.-K. Zhao , Center for Reliable & High Performance Comput., Illinois Univ., Urbana, IL, USA
pp. 288
SESSION 14: MIXED SIGNAL TEST

Automated test pattern generation for analog integrated circuits (Abstract)

G. Gielen , ESAT, Katholieke Univ., Leuven, Heverlee, Belgium
G. Van der Plas , ESAT, Katholieke Univ., Leuven, Heverlee, Belgium
W. Verhaegen , ESAT, Katholieke Univ., Leuven, Heverlee, Belgium
pp. 296

A DFT Technique for Analog-to-Digital Converters with digital correction (Abstract)

Jose L. Huertas , Instituto de Microelectr_nica de Sevilla (IMSE-CNM) email: rueda@cnm.us.es
Eduardo Peralias , Instituto de Microelectr_nica de Sevilla (IMSE-CNM) email: rueda@cnm.us.es
Adoracion Rueda , Instituto de Microelectr_nica de Sevilla (IMSE-CNM) email: rueda@cnm.us.es
pp. 302

Determination of coherence errors in ADC spectral domain testing (Abstract)

W.D. Bartlett , Data Acquistion Products Test Engineer, FL, USA
pp. 308
PANEL SESSION 3:
PANEL SESSION 4:
PANEL SESSION 5:
SESSION 15: SEQUENTIAL CIRCUITS TEST II

Testability of Sequential Circuits with Multi-Cycle False Paths (Abstract)

Priyank Kalla , University of Massachusetts
Maciej Ciesielski , University of Massachusetts
pp. 322

EXTEST: a method to extend test sequences of synchronous sequential circuits to increase the fault coverage (Abstract)

S.M. Reddy , Dept. of Electr. & Comput. Eng., Iowa Univ., Iowa City, IA, USA
I. Pomeranz , Dept. of Electr. & Comput. Eng., Iowa Univ., Iowa City, IA, USA
pp. 329

On n-detection test sequences for synchronous sequential circuits (Abstract)

S.M. Reddy , Dept. of Electr. & Comput. Eng., Iowa Univ., Iowa City, IA, USA
I. Pomeranz , Dept. of Electr. & Comput. Eng., Iowa Univ., Iowa City, IA, USA
pp. 336
SESSION 16: ON-LINE TESTING AND FAULT-TOLERANT DESIGN

An on-line testable UART implemented using IFIS (Abstract)

S. Jones , Dept. of Electron. & Electr. Eng., Loughborough Univ. of Technol., UK
J. Yeandel , Dept. of Electron. & Electr. Eng., Loughborough Univ. of Technol., UK
D. Thulborn , Dept. of Electron. & Electr. Eng., Loughborough Univ. of Technol., UK
pp. 344

A linear code-preserving signature analyzer COPMISR (Abstract)

A. Hlawiczka , Inst. of Electronics., Silesian Tech. Univ., Gliwice, Poland
M. Gossel , Inst. of Electronics., Silesian Tech. Univ., Gliwice, Poland
E.S. Sogormonyan , Inst. of Electronics., Silesian Tech. Univ., Gliwice, Poland
pp. 350

A high-level synthesis approach to design of fault-tolerant systems (Abstract)

M.G. Sami , Dipt. di Elettronica, Politecnico di Milano, Italy
M. Pugassi , Dipt. di Elettronica, Politecnico di Milano, Italy
G. Buonanno , Dipt. di Elettronica, Politecnico di Milano, Italy
pp. 356
SESSION 17: SCAN AND BOUNDARY SCAN

ATPG for scan chain latches and flip-flops (Abstract)

S.R. Maka , Center for Reliable Comput., Stanford Univ., CA, USA
E.J. McCluskey , Center for Reliable Comput., Stanford Univ., CA, USA
pp. 364

High-Level Synthesis for Orthogonal Scan (Abstract)

Edward J. McCluskey , Stanford University
Robert B. Norwood , Stanford University
pp. 370
SESSION 18: TESTABILITY ANALYSIS

A methodolgy for characterizing cell testability (Abstract)

F.J. Ferguson , Semicond.. Diagnosis & Test, Mipitas, CA, USA
A. Jee , Semicond.. Diagnosis & Test, Mipitas, CA, USA
pp. 384

Fault coverage of a long random test sequence estimated from a short simulation (Abstract)

V. Prepin , Lab. d Autom. de Grenoble, France
R. David , Lab. d Autom. de Grenoble, France
pp. 391

Random pattern testability of memory control logic (Abstract)

J. Savir , Dept. of Electr. & Comput. Eng., New Jersey Inst. of Technol., Newark, NJ, USA
pp. 399
SESSION 19: BIST II

Salvaging test windows in BIST diagnostics (Abstract)

J. Savir , Dept. of Electr. & Comput. Eng., New Jersey Inst. of Technol., Newark, NJ, USA
pp. 416

On Optimizing BIST-Architecture by Using OBDD-based Approaches and Genetic Algorithms (Abstract)

Martin Keim , Institute of Computer Science Albert-Ludwigs-University
Rolf Krieger , Institute of Computer Science Albert-Ludwigs-University
Bernd Becker , Institute of Computer Science Albert-Ludwigs-University
Can Oekmen , Institute of Computer Science Albert-Ludwigs-University
pp. 426
SESSION 20: THERMAL & ELEVATED VOLTAGE TESTING

Differential Sensing Strategy for Dynamic Thermal Testing of ICs (Abstract)

Josep Altet , Universitat Politecnica de Catalunya
Antonio Rubio , Universitat Politecnica de Catalunya
pp. 434

Integrating on-chip temperature sensors into DfT schemes and BIST architectures (Abstract)

M. Rencz , Dept. of Electron Devices, Tech. Univ. Budapest, Hungary
B. Courtois , Dept. of Electron Devices, Tech. Univ. Budapest, Hungary
V. Szekely , Dept. of Electron Devices, Tech. Univ. Budapest, Hungary
pp. 440

SHOrt voltage elevation (SHOVE) test for weak CMOS ICs (Abstract)

J.T.Y. Chang , Center for Reliable Comput., Stanford Univ., CA, USA
E.J. McCluskey , Center for Reliable Comput., Stanford Univ., CA, USA
pp. 446
PANEL SESSION 6:
PANEL SESSION 7:
PANEL SESSION 8:

Author Index (PDF)

pp. 465
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