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2013 IEEE 31st VLSI Test Symposium (VTS) (1997)
Monterey, California
Apr. 27, 1997 to May 1, 1997
ISBN: 0-8186-7810-0
pp: 196
A method to perform diagnostic test generation in sequential circuits by modifying a conventional test generator is presented. The method utilizes circuit netlist modification along with a forced value at a primary input in the modified circuit. Techniques to reduce the computational effort for diagnostic test pattern generation in sequential circuits are also presented. Speeding up the diagnostic ATPG process is achieved by the identification of states that are impossible to justify with three-valued logic.
Vamsi Boppana, W. Kent Fuchs, Janak H. Patel, Ismed Hartanto, hartanto@dtc.hp. com, "Diagnostic Test Pattern Generation for Sequential Circuits", 2013 IEEE 31st VLSI Test Symposium (VTS), vol. 00, no. , pp. 196, 1997, doi:10.1109/VTEST.1997.600264
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