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2013 IEEE 31st VLSI Test Symposium (VTS) (1997)
Monterey, California
Apr. 27, 1997 to May 1, 1997
ISBN: 0-8186-7810-0
pp: 188
Janak H. Patel , Center for Reliable and High-Performance Computing University of Illinois, Urbana, IL http://www.crhc.uiuc.edu/
Elizabeth M. Rudnick , Center for Reliable and High-Performance Computing University of Illinois, Urbana, IL http://www.crhc.uiuc.edu/
Michael S. Hsiao , Center for Reliable and High-Performance Computing University of Illinois, Urbana, IL http://www.crhc.uiuc.edu/
ABSTRACT
Two fast algorithms for static test sequence compaction are proposed for sequential circuits. The algorithms are based on the observation that test sequences traverse through a small set of states, and some states are frequently re-visited throughout the application of a test set. Subsequences that start and end on the same states may be removed if necessary and sufficient conditions are met for them. The techniques require only two fault simulation passes and are applied to test sequences generated by various test generators, resulting in significant compactions very quickly for circuits that have many revisited states.
INDEX TERMS
inert subsequence, recurrence subsequence, test set compaction
CITATION
Janak H. Patel, Elizabeth M. Rudnick, Michael S. Hsiao, "Fast Algorithms for Static Compaction of Sequential Circuit Test Vectors", 2013 IEEE 31st VLSI Test Symposium (VTS), vol. 00, no. , pp. 188, 1997, doi:10.1109/VTEST.1997.600260
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